a question on the xtal osc deisgn

[chang830]

Hi

We are deisgning a 35MHz xtal osc. The attached file is the schematic of the ciruit we used. It is a typical cross-coupled oscillator.

The negative impedence anlaysis is OK. But I can not make it oscillate.

Would anyone pls. tell me any wrong with the schematic? Is ithis topology suitble for the crystal osc deisgn?

Thanks in advance

 

[erikl]

Re: a question on the xtal osc design

The negative impedence anlaysis is OK. But I can not make it oscillate.

Would anyone pls. tell me any wrong with the schematic? Is this topology suitible for the crystal osc design?

I guess your double-feedback loop renders the circuit too stable. Try to use the nfets as diodes (i.e. connect their gates to their own drains).

 

[chang830]

Re: a question on the xtal osc design

The negative impedence anlaysis is OK. But I can not make it oscillate.

Would anyone pls. tell me any wrong with the schematic? Is this topology suitible for the crystal osc design?

I guess your double-feedback loop renders the circuit too stable. Try to use the nfets as diodes (i.e. connect their gates to their own drains).

Thanks for the reply!

My question is where is the negative impedence if we connect their gates to their own drains?

Thanks

 

[erikl]

Re: a question on the xtal osc design

My question is where is the negative impedance if we connect their gates to their own drains?

I think the pos. feedback via the cross-coupled pfets should be enough. Same as for a FF. Suggest to try it!

 

[tdy]

size up the transistors

 

[saro_k_82]

I think you got the motivation from the popular LC oscillator. Fine but there L provides dc feedback to establish proper bias points. The inductance makes sure that the positive feedback loop gain for dc is low and so it is dc stable. Whereas in the schematic you have provided, the loop gain at dc is huge so some of the transistors will be in linear region --> no oscillation.

 

[chang830]

I think you got the motivation from the popular LC oscillator. Fine but there L provides dc feedback to establish proper bias points. The inductance makes sure that the positive feedback loop gain for dc is low and so it is dc stable. Whereas in the schematic you have provided, the loop gain at dc is huge so some of the transistors will be in linear region --> no oscillation.

Thanks for the useful reply. It does help me.

I intend to add a large resistor(about 50MOhm) parallel with the xtal to provide this dc bias. What do you think? Any risks?

Thanks

 

[saro_k_82]

No wait. Such a large resistor would be costly (if implemented on-chip) and would reduce the Q, add noise and the oscillator may not startup in all corners.
There is a much more elegant solution to the problem.
Just think of this structure.., Have a cross coupled negative gm generating nmos pair and instead of shorting the two sources, connect them with a capacitor. The two sources are biased with two matched current sources. The xtal is connected between the two drains and the drains are biased with two matched resistors to VDD (This can be replaced with current sources if required).
Now the capacitor makes the circuit dc stable and a proper capacitor value makes the circuit oscillate at the crystal frequency.
The two tail current sources can get their bias from the drains after some filtering., making the circuit self-sufficient and extremely low phase noise. The power consumption will be very low as well.
I read a paper on this some time back and have simulated the performance., I found this to be a very useful and interesting architecture.
I'll upload it if I find it now.

Adv:
1. Balanced sine wave output swings at the pad. No current in to the ESD diodes
2. Does not require loading caps by design, but one might include them to get better temperature and ageing characteristics.
3. Does not corrupt the supply/substrate and tolerant to supply/substrate noise.
4. Very low phase noise
5. Very low power

Disadv:
1. Requires an extra on-chip capacitor
2. Requires two pads
3. The structure is also a relaxation mode oscillator (without the xtal) and one needs to select the capacitor to avoid it (or there are other tricks here). There is no catastrophe if this mode exists as well., but it is better to avoid it.

Thanks,
Saro

 

[strabush]

Are you sure it will not oscillate? What kind of Xtal parameters do you use? Real xtal parameters? the wake-up time might be very very long because of the Xtal very high Q factor. One way to check this point is to lower the Q by increasing C and decresing L of the series LC by a few orders. Another way is to start the simulation with voltage and current initial conditions that are to be expected when the circuit is at stedy state oscillations, for example v(C) = -V(L) and I(C) = I(L).

 

[dick_freebird]

Simulation of XOs is tricky, I've had a lot of trouble
with it. Problem #1 is startup where the level of real
oscillation may be less than numerical accuracy and
it just "gets lost in the hoise" before it can climb out
of its hole.

Xtals store very little energy and anything that has a
conductance, is the enemy. You may find that the
driver needs to have long channel devices, the input
ESD leakage costs you tank energy, etc. Any sort
of feedback scheme (like centering the input) should
be very low current / high impedance.

You might find it interesting to try driving the thing
open loop -through- the crystal with a sine source,
then break that off and see how long the tank can
sustain, and what may be bleeding its energy from
the input side.

 

[saro_k_82]

You guys are overlooking a more fundamental requirement for oscillation., dc stability.
If you take a wien bridge oscillator and swap the Zf and Z1 of the positive feedback side, the center frequency, Q, etc does not change, but will it oscillate? NO.
Any crystal oscillator due to it's large Q, can take a lot of time to settle but it would be able to sustain or grow oscillations from an initial disturbance which would have progressively larger energy (until it settles) than the initial disturbance. This is not possible in this architecture shown by chang830

 

[chang830]

No wait. Such a large resistor would be costly (if implemented on-chip) and would reduce the Q, add noise and the oscillator may not startup in all corners.
There is a much more elegant solution to the problem.
Just think of this structure.., Have a cross coupled negative gm generating nmos pair and instead of shorting the two sources, connect them with a capacitor. The two sources are biased with two matched current sources. The xtal is connected between the two drains and the drains are biased with two matched resistors to VDD (This can be replaced with current sources if required).
Now the capacitor makes the circuit dc stable and a proper capacitor value makes the circuit oscillate at the crystal frequency.
The two tail current sources can get their bias from the drains after some filtering., making the circuit self-sufficient and extremely low phase noise. The power consumption will be very low as well.
I read a paper on this some time back and have simulated the performance., I found this to be a very useful and interesting architecture.
I'll upload it if I find it now.

Adv:
1. Balanced sine wave output swings at the pad. No current in to the ESD diodes
2. Does not require loading caps by design, but one might include them to get better temperature and ageing characteristics.
3. Does not corrupt the supply/substrate and tolerant to supply/substrate noise.
4. Very low phase noise
5. Very low power

Disadv:
1. Requires an extra on-chip capacitor
2. Requires two pads
3. The structure is also a relaxation mode oscillator (without the xtal) and one needs to select the capacitor to avoid it (or there are other tricks here). There is no catastrophe if this mode exists as well., but it is better to avoid it.

Thanks,
Saro

Dear Saro,
Sorry for my late thanks because I am trying the archetecture you advused in these days.

Yes, it becomes the relaxation osc when the capacitor is not properly selected
and the frequency depends on the RC instead of xtal. It is not expected in our case because it is used as the reference frequency in our wireless receiver.

I wonder how to properly select the valuse of capacitor? I am trying alll the ways but it seemed not work well.
I also try to google the paper you mentioned above, but i failed o to find it.

Would you pls. give us some more help?

Thanks

 

[saro_k_82]

I did not find it difficult at all to keep it off from relaxation mode. There is a max limit on the capacitor set by the relaxation mode and min limit set by the necessity to have negative resistance at 35MHz. You can find them through simulation.

I have attached the architecture I used and the relevant papers.

 

[chang830]

I did not find it difficult at all to keep it off from relaxation mode. There is a max limit on the capacitor set by the relaxation mode and min limit set by the necessity to have negative resistance at 35MHz. You can find them through simulation.

I have attached the architecture I used and the relevant papers.

Dear saro,

Yes, we are happy to tell you we can make it work now! We have some misuderstandings on it previously.

We are optimizing the circuit and will let you konw the progress.

We realy appreciate your kindness.