pll sdm clock
advaita said:
BTW, why are you planning for an eight level dac. I think it'll increase your period jitter as compared to fewer number of levels. What do you say?
I don't see any plans of using a dac at all in the original post, only a digital MASH sigma delta modulator (sdm) controlling a mulimodulus divider.
But back to the question; I am not really certain what would be the correct answer, but I could come with some inputs.
First of all it is important to realise that a fractional PLL (mash111) is newer really locked when you look at it in the time domain. That is the frequency is constantly jumping up and down with an average identical to your programmed frequency, so looking for a phase error might be some troublesome.
But you usually interprets the output from the first accumulator (for a 1st order sdm) as the phase error vs. time. So looking at this your phase error constantly rotates from zero to 2pi with the resolution of your fractional input (eg 1000 / 2^20 for a 20 bit accumulator).
If you have a 2nd order sdm the output of the second accumulator represents the integrated phase error, so you would have to make 1 differentiation of the output to get the phase error and 2 differentiations for a 3rd order sdm, and so forth.
It is a good lesson to look at these outputs and looking for periodicity (ie one possible origin for spurs) and notice how the phase error is 'randomized' as the sdm order is increased.