due to channel lenght modulation there is no channel at the drain side of MOS when it is biased in deep saturation region, so the overlap capacitance between gate and drain get added with oxide capacitance bcoz under gate oxide surface at drain end there is a depletion region which act as insulator and over all capacitance included gate drain overlap capacitance.
An easy way to think about it is that now you have one plate (your gate), you have dielectric (SiO2) but your bottom plate (channel) is missing at drain side due to channel length modulation. That's why your Cgd now is nearly zero.