Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

a question about the amplitude of vco

Not open for further replies.


Newbie level 4
Dec 12, 2009
Reaction score
Trophy points
Activity points
Dear guys:
I am confused that some pappers say the maximum output of the vco is 2VDD.
the vco ,e.g with nmos or complementary differential-couple LC oscillator operated in voltage-limitted region , the maximum differential output of it is from -VDD to + VDD,thus the maximum differential output amplitude is VDD rather than 2VDD,what 's wrong with my result?
thanks a lot.:?:
Last edited:

Well, you said it yourself. If the differential voltage goes from -V to +V, then the peak to peak voltage across a load will be 2 V. It is a little clearer if you add a balun to the output pins and convert to a single ended output, like a lot of wireless chips do.

Another way to get a higher voltage than the supply is to use some sort of tank circuit. The transistor only conducts for a short portion of the sine wave, and the L-C or other tank circuit "rings" at a high voltage.

thank you for your replying,biff44.
i found the error of my thought.Indeed,the maximum single-end output range is from 0 to 2VDD rather than 0 to VDD.
in my previous calculation ,i use the drain current of the differential-coupled pair multiply Rp to calculate the output voltage.
The current is comprise of quiescent current and transient current and the Rp is short to the quiescent current.

Not open for further replies.

Part and Inventory Search

Welcome to