assura_dv_design_rule_checker
[root@server license]# lmgrd -c license.dat
Incorrectly built binary which accesses errno or h_errno directly. Needs to be f ixed.
2:10:28 (lmgrd) -----------------------------------------------
2:10:28 (lmgrd) Please Note:
2:10:28 (lmgrd)
2:10:28 (lmgrd) This log is intended for debug purposes only.
2:10:28 (lmgrd) There are many details in licensing policies
2:10:28 (lmgrd) that are not reported in the information logged
2:10:28 (lmgrd) here, so if you use this log file for any kind
2:10:28 (lmgrd) of usage reporting you will generally produce
2:10:28 (lmgrd) incorrect results.
2:10:28 (lmgrd)
2:10:28 (lmgrd) -----------------------------------------------
2:10:29 (lmgrd)
2:10:29 (lmgrd)
2:10:29 (lmgrd) lmgrd running as root:
2:10:29 (lmgrd) This is a potential security problem
2:10:29 (lmgrd) And is not recommended
[root@server license]# 2:10:29 (lmgrd) FLEXlm (v8.4a) started on server (linux) (8/7/2005)
2:10:29 (lmgrd) Copyright (c) 1988-2003 by Macrovision Corporation. All rights reserved.
2:10:29 (lmgrd) US Patents 5,390,297 and 5,671,412.
2:10:29 (lmgrd) World Wide Web: **broken link removed**
2:10:29 (lmgrd) License file(s): license.dat
2:10:29 (lmgrd) lmgrd tcp-port 5280
2:10:29 (lmgrd) Starting vendor daemons ...
2:10:29 (lmgrd) Started cdslmd (internet tcp_port 32771 pid 3350)
Incorrectly built binary which accesses errno or h_errno directly. Needs to be f ixed.
2:10:29 (cdslmd) FLEXlm version 8.4a
2:10:29 (cdslmd) Server started on server for: 100
2:10:29 (cdslmd) 21900 26000 Affirma_sim_analysis_env
2:10:29 (cdslmd) CWAVES UET VERILOG-XL
2:10:29 (cdslmd) VXL-VCW VXL-VET VXL-VLS
2:10:29 (cdslmd) VXL-VRA 111 11400
2:10:29 (cdslmd) 12141 200 206
2:10:29 (cdslmd) 207 21060 LEAPFROG-CV
2:10:29 (cdslmd) 21400 276 278
2:10:29 (cdslmd) Composer_Spectre_Sim_Solution 283 300
2:10:29 (cdslmd) 3000 Virtuoso_XL 302
2:10:29 (cdslmd) Virtuoso_Schem_Option 305 32100
2:10:29 (cdslmd) OASIS_Simulation_Interface 32120 Artist_Statistic s
2:10:29 (cdslmd) 32125 Corners_Analysis 32130
2:10:29 (cdslmd) Artist_Optimizer 32140 32150
2:10:29 (cdslmd) 32190 32500 32501
2:10:29 (cdslmd) 32510 32520 SpectreRF
2:10:29 (cdslmd) 32521 Affirma_RF_SPW_model_link 32530
2:10:29 (cdslmd) Affirma_RF_IC_package_modeler 32550 32760
2:10:29 (cdslmd) 33010 33011 Device_Level_Placer
2:10:29 (cdslmd) 33015 Virtuoso_Core_Optimizer 33016
2:10:29 (cdslmd) Virtuoso_Core_Characterizer 33301 34500
2:10:29 (cdslmd) 34510 34511 Substrate_Coupling_Analysis
2:10:29 (cdslmd) 34515 34520 34525
2:10:29 (cdslmd) 34530 Affirma_AMS_distrib_processing 370
2:10:29 (cdslmd) 371 37100 373
2:10:29 (cdslmd) 374 LAS_Cell_Optimization 37500
2:10:29 (cdslmd) Device_Level_Router 41000 501
2:10:29 (cdslmd) 550 570 940
2:10:29 (cdslmd) 945 952 Composer_EDIF300_Connectivity
2:10:29 (cdslmd) 953 Composer_EDIF300_Schematic BTAHVMOS
2:10:29 (cdslmd) Spectre_BTAHVMOS_Models BTASOI Spectre_BTASOI_M odels
2:10:29 (cdslmd) NTMODELS Spectre_NorTel_Models SpectreBasic
2:10:29 (cdslmd) STMODELS Spectre_ST_Models 11701
2:10:30 (cdslmd) 11702 11703 11710
2:10:30 (cdslmd) DRACSLAVE DRACDIST DRAC2CORE
2:10:30 (cdslmd) 12500 14000 _21900
2:10:30 (cdslmd) 14010 14020 14040
2:10:30 (cdslmd) 14050 EBD_power EBD_edit
2:10:30 (cdslmd) EBD_floorplan ALL_EBD 14060
2:10:30 (cdslmd) Datapath_Preview_Option 14065 Datapath_Verilog
2:10:30 (cdslmd) 14066 Datapath_VHDL 14070
2:10:30 (cdslmd) Preview_Synopsys_Interface 14101 14111
2:10:30 (cdslmd) 14120 14130 14140
2:10:30 (cdslmd) 14300 14400 14410
2:10:30 (cdslmd) 312 314 316
2:10:30 (cdslmd) 318 322 336
2:10:30 (cdslmd) 365 51020 FPGA_Flows
2:10:30 (cdslmd) FPGA_Tools xilEdif xilConceptFE
2:10:30 (cdslmd) xilCds 51021 51022
2:10:30 (cdslmd) xilComposerFE PIC_Utilities 51023
2:10:30 (cdslmd) 51070 51100 51170
2:10:30 (cdslmd) 681 ConcICe_Option 70110
2:10:30 (cdslmd) DRACERC DRAC3DRC Distributed_Dracula_Opti on
2:10:30 (cdslmd) 70120 DRAC3LVS DRACLVS
2:10:30 (cdslmd) 70130 DRACLPE DRACPRE
2:10:30 (cdslmd) 70510 70520 71110
2:10:30 (cdslmd) Assura_DV_design_rule_checker 71120 Assura_DV_LVS_ch ecker
2:10:30 (cdslmd) 71130 Assura_DV_parasitic_extractor 71510
2:10:30 (cdslmd) 71520 727 728
2:10:30 (cdslmd) 729 730 DRACPLOT
2:10:30 (cdslmd) 731 DRAC2DRC 733
2:10:30 (cdslmd) DRAC2LVS 761 763
2:10:30 (cdslmd) DRAC3CORE 780 DRACPG_E
2:10:30 (cdslmd) 785 DRACACCESS 792
2:10:30 (cdslmd) 920 950 960
2:10:30 (cdslmd) 963 964 965
2:10:30 (cdslmd) 966 972 974
2:10:30 (cdslmd) 12110 12111 900
2:10:30 (cdslmd) 50200
2:10:30 (cdslmd)
2:10:30 (cdslmd) All FEATURE lines for this vendor behave like INCREMENT lines
2:10:30 (cdslmd)
Above is the results when I run command lmgrd -c license.dat.
What shall I do next?
Thanks.