a problem related to multi_finger structure--- how strange!

[sunjiao3]

Hi, dear all.
I encountered a strange problem in the multi_finger structure. In simulating a hysteresis comparator, I found that the width of the hysteresis window and the tolerence of mismatch is closely related to the number of the fingers. In addition, even the structure with the same numbers of fingers, have different simulation result. For example, a nmos, which is 10/2, is depatched into a 2*5/2 with 2 fingers or 2 mos transistors each sized 5/2. The results are different. Why?
I know it is related to the physics of the mos transistor. So, could anyone please shed light on this problem. BTW, the comparator work in low frequency, so, the Cgd and Cgs are not so important, in my opinion.
Also, is there any thesis focused on this topic? I would like to know some details of it.
Thank you very much.

 

[rfsystem]

Re: a problem related to multi_finger structure--- how stra

The common understanding is that the total gate area models the threshold and conductance mismatch. If you use an automated mismatch analysis eg. spectre it use the process mismatch setting in the model file. Possible either spectre does not consider M>1 or you use instead of a single instance in the netlist with M>1 a number of parallel connected instances. The automated mismatch analysis then have to sum up the instances. So please look how the mismatch paramters are derived.

 

[sunjiao3]

Re: a problem related to multi_finger structure--- how stra

Here, I didn't use the automatic mismatch analyse in spectre. I just change the size of one of the differential pairs. If I use no finger, with a mismatch of 5% or so, the hysteresis disappeared. However, with the use of fingers, the hysteresis remained with even 150%(of course, such huge mismatch is impossible in reality.)
Any thesis or books on this topic?

 

[rfsystem]

Re: a problem related to multi_finger structure--- how stra

If you change the size of the differential pair, does that mean changing one instance of a symmetric pair? Or did you mean changing the size all input relevant devices?

 

[sunjiao3]

Re: a problem related to multi_finger structure--- how stra

rfsystem, I mean the former.

 

[skal81]

Re: a problem related to multi_finger structure--- how stra

You should check your spice model file. In BSIM3 there is differents set of parameters depending on the W and L.
This means that a transistor with W=10 use one set with one value for Vth and so,
and W=5 finger=2 use another.
Further more, the parameters are adjusted depending on the W and L. So it leads to different results when using finger or parallel transistor.
If you want to see the details refer to the BSIM documentation.

Anyhow I think the best is to enter the parameter that will be the closest to the layout. So I personnaly don't use W=100 or more, but W=5, finger = 2 and 10 parallel transistor.
But be carefull when paralleling transistor. Use the m parameter. If you really put parrallel on the schematic it increases the node number and make the simulation slower.

 

[sunjiao3]

Re: a problem related to multi_finger structure--- how stra

skal81, thank you very much for enlighting me on this topic.
However, there is another point I wanna mention here. As you said, using fingers or parallel transistors may lead to different result after simulation. So, the way to write netlist or schematic need our pondering. Usually, the differences of these 2 ways of layout are thought to be their Cgd and Cgs. As a result, I was told, "there won't be many differences between them in low frequency." However, in simulation, I found that in some DC case, the results of the simulation are different. Atention, I used same fingers. For example, for a w=10 transistor, I uses a transistor with 2 fingers and w=5, or, 2 transistors each with one finger, w=5. The fingers of these 2 ways are the same: 2=2*1. Thus, their resistance of the gate are the same theoretically. So, where comes the differences in DC simulation?

 

[Fom]

Re: a problem related to multi_finger structure--- how stra

skal81 explained to you

This means that a transistor with W=10 use one set with one value for Vth and so, and W=5 finger=2 use another.

That's why your DC simulation results are different.

 

[rfsystem]

Re: a problem related to multi_finger structure--- how stra

Sorry I got confused. I thougth the discussion is about a difference in the mismatch! Not the difference between W1~W2*M. The width effect of a MOS could be seen by the printout of the effective width. But this should have only a very minor effect on the mismatch result.

Please clearify!

 

[sunjiao3]

Re: a problem related to multi_finger structure--- how stra

rfsystem, it is not about mismatch. Here, no differential pairs or so are talked. The focus is on the different simulation result I got using different arrangement of a mos transistor in layout. It is about the different of fingers and dispatching.

 

[skal81]

Re: a problem related to multi_finger structure--- how stra

As Fom pointed out the DC spice model parameters are also affected by W and L. I just wrote Vth, but in fact all the parameters, with more or less. So there is no surprise your DC and AC simulation results change.
So really do your schematic as close as you'll do your layout. First you'll get more accurate simulation results, secondly when doing the layout and LVS it will be easier