No one
Full Member level 5
Hello Everyone;
I have designed a fractional PLL circuit using ADF4156 of Analog Devices, but it has two problem:
1) It has two spurs about ±25kHz apart from the desired carrier that are about 20-30dBc below carrier.
2) It's lock time isn't good.
Please help me.
I have designed a fractional PLL circuit using ADF4156 of Analog Devices, but it has two problem:
1) It has two spurs about ±25kHz apart from the desired carrier that are about 20-30dBc below carrier.
2) It's lock time isn't good.
Please help me.