Jul 25, 2006 #1 W wildwood Junior Member level 2 Joined Jul 1, 2005 Messages 20 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,568 I'm using the ARM7TDMI Design Simulation Module . the sdm is integreted in a digital design , and finished the synthesis . I meet a problem when i transtlate the verilog netlist into spice netlist . I use nettran command in hercules to do this , for the standard cell , i have the cdl file to map the verilog netlist to transister-level , but I don't know what to do with the ARM7TDMI DSM . Is there anyone can give me any hints ? thx in advance !
I'm using the ARM7TDMI Design Simulation Module . the sdm is integreted in a digital design , and finished the synthesis . I meet a problem when i transtlate the verilog netlist into spice netlist . I use nettran command in hercules to do this , for the standard cell , i have the cdl file to map the verilog netlist to transister-level , but I don't know what to do with the ARM7TDMI DSM . Is there anyone can give me any hints ? thx in advance !