-- Generic at top-level
DESIGN_RELEASE_TYPE : unsigned(7 downto 0) := to_unsigned( 0, 8);
DESIGN_RELEASE_MAJOR : unsigned(7 downto 0) := to_unsigned( 0, 8);
DESIGN_RELEASE_MINOR : unsigned(7 downto 0) := to_unsigned( 1, 8)
-- Signal declarations area
constant FPGA_DESIGN_VERSION : unsigned(31 downto 0) := x"A7" & DESIGN_RELEASE_TYPE & DESIGN_RELEASE_MAJOR & DESIGN_RELEASE_MINOR;
signal fpga_design_version_s : std_logic_vector(31 downto 0):= std_logic_vector(FPGA_DESIGN_VERSION);
-- Portmap area
.
.
fpga_design_version_i => fpga_design_version_s ,
.
.