A Johnson counter in VHDL

[Jorge Jesse Cantu]

With the following specifications:

Design a 4-bit Johnson counter and decoding for all eight states using just four flip-flops and eight gates. Your counter needs not be self-correcting.

I wrote my VHDL code for the 4-bit Johnson counter, but I am confused as to what it means by decoding for all eight states, using eight gates? Do I need to have combinational logic to implement this? If so, how would I implement that in vhdl?

Here is my code:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;

entity eightRC is 

 port(
        CLK : in    std_logic;
        EN: in  std_logic;
        RST : in    std_logic;
        Q: out  std_logic_vector(7 downto 0)
    );

end eightRC;

architecture behavior of eightRC is
signal qs: std_logic_vector(7 downto 0);
begin
    process(CLK, RST, EN)
    begin 
        if(RST = '1') then
            QS <= "11111110";       --initial state for QS
      elsif (CLK'EVENT AND CLK = '1' and EN = '1') then     --enable starts the shifting
         QS(0) <= QS(7);            --shift '0' to the left each clock edge, Q(0) gets Q(0) bit value
         QS(7 downto 1) <= QS(6 downto 0);
      end if;                      
    Q <= QS;
    end process;
end behavior;

 

[shahulakthar]

here it is.

 

[FvM]

Your code doesn't describe a 4-bit Johnson counter. This is it https://electronics-course.com/johnson-counter

QS(3 downto 0) <= Q(2 downto 0) & not (Q3);

 

[imbichie]

Hi,

It seems to be an 8 bit counter.
"Q: out std_logic_vector(7 downto 0)"

 

[Jorge Jesse Cantu]

Update: I did something dumb and posted the wrong code first, here is the right code:

with the following specifications:

Update: I did something dumb and posted the wrong code first, here is the right code:

design a 4-bit johnson counter and decoding for all eight states using just four flip-flops and eight gates. Your counter needs not be self-correcting.


i wrote my vhdl code for the 4-bit johnson counter, but i am confused as to what it means by decoding for all eight states, using eight gates? Do i need to have combinational logic to implement this? If so, how would i implement that in vhdl?

Here is my code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity json_cnter is
port ( 
        q : Out std_logic_vector(3 downto 0);
        rst : In std_logic;
        clk : In std_logic
        );
end json_cnter;

architecture behavior of json_cnter is

signal shft_r : Std_logic_vector (3 downto 0);-- :=(others => '0');

begin
q <= shft_r;
process(clk)
begin
    if(clk'event and clk = '1') then
        if (rst = '1') then
            shft_r <= (others => '0');	
        else
            shft_r(1) <= shft_r(0);		--shift bits to the right
            shft_r(2) <= shft_r(1);
            shft_r(3) <= shft_r(2);
            shft_r(0) <= not shft_r(3);
        end if;
    end if;
end process;
    
end behavior;