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# A GFSK demodulator for low-IF Bluetooth receiver

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#### promach

For , how does the shape-keeping circuit in figure 4(c) works ?

Besides, why need the NOR gate before the input to the shape-keeping circuit ?

Figure C has a memory cell made from 2 NOR gates.
The op amps create a window comparator.
I'm guessing the rightmost section creates reliably uniform pulses, identical amplitude and identical slew rate.

Figure A appears to output PWM (or else PFM) based on how incoming waveforms overlap or don't overlap. Where numerous simple logic gates are cascaded it becomes hard to be sure whether they perform the job of a more complex gate, or whether they invert a signal to make it compatible with the following stage.

How does the IQ signals look like for modulated GFSK signal ?

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Q is shifted by 90 degrees wrt I.
Both are sinusoid with frequency in range 0.33IF to 1.65IF, depending on modulation index (0 has lower frequency, 1 has higher).

### promach

Points: 2
Why frequency in range 0.33IF to 1.65IF ??

By the way, have a look at page 134 and page 135 of **broken link removed**
which will determine how the I and Q channels inputs actually look like in the circuit

#### Attachments

• GFSK.zip
461.2 KB · Views: 113

Hi,

What should we look for?
I see unconnected inputs.

Klaus

@KlausST Which exact inputs are unconnected ??

R1 R2 R3 create a voltage divider which provides reference voltages. I think their value can be higher ohms, say 1k.

R9 is 100 ohms. M1 turns on thus providing some resistance to ground. The node between them feeds C6 and U2 input. If you want to create a middle range of voltage swing, then it requires M1 must turn on so its resistance becomes 100 ohms (and less). It may not do this easily. I think R9 could probably be 1k.

What is the purpose of the RC components inside zero-crossing detection circuit (Figure 4(b) ZD one-Shot) ?

Which exact inputs are unconnected ??
Almost at every logic gate...

Klaus

@KlausST LTSpice only have 5-inputs logic gate, so not connecting every inputs of the logic gate is allowed.

Hi,

I did some internet search. It seems you are right.
They even recommend to short circuit unused outputs to GND. Good luck for real life circuits.

My personal opinion:
* simulators should work like real world devices work ... most perfectly
* it's not unusual that one uses a 4 input logic IC but uses only 3 inputs..then one simply has to give valid input levels to the unused inputs. This is real life and makes sense. Giving "GND" to an unused AND input makes the circuit useless..but the simulator is happy.

Especially for unexperienced users simulators are very helpful, enabling tests on circuits without smoke and awful smell.
But they were thought "wrong" usage. I see simulators work even when power is not supplied to the ICs, clock inputs not connected,
Imagine: Teach pupils in school that 3 x 4 = 12, but the calculator gives a different result...

Klaus

Note: pseudo transient analysis issue means that the simulator is stucked with running pseudo transient analysis forever without any output waveform results.

The pseudo transient analysis issue happens only when I replace the OR gates (A5, A6, A9, A11) in favour of NOR gates inside the ZD one-shot circuit blocks.

#### Attachments

• GFSK_draft_use_OR_gate_without_psuedo_transient_analysis_issue.zip
4.4 KB · Views: 93
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I isolated the ZD one-shot circuit and then tried to ground the output of the NOR gates, but the pseudo transient analysis issue still persists. Why ?

I found a good way to debug this pseudo transient analysis issue.

Try increasing C1,C2,C3,C4 to 150pF and then changing either (A5,A6) or (A9,A11) branches to use NOR gates.
Then the issue will be gone temporarily, the root cause is still under investigation.

Remember NOT to allow BOTH branches to use NOR gates.

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