The "Analog Input Bandwidth of 500MHz Max" is related to the differential analog input stage, that has a 3-dB bandwidth that extends up to 500 MHz.
In other words, you can put a signal with frequencys up to 500 Mhz through the input stage and have a maximum 3 dB attenuation. Please see Figure 41 and 42 at page 32 in the datasheet.
This is a 14 bit 170 Mega samples per second A/D, so the equivalent bit rate is 14*170=2380 Mega bits per second(2.38 Gbps).
For you to respect the Nyquist criteria the maximum frequency you can have at the input is (Sampling rate)/2, so in this case is 170/2=85 Mhz.
It is your responsability to make sure that the Nyquist criteria is respected (use low pass filters or other method) in your system.
It is not necessary to limit band width of a signal which is being sampled.
Not doing so will result in a so called sampling mixer.
Baisicly, You will sample aliases. E.g. consider an input signal having a carrier of 10.7MHz. Sampling such a signal with ADC clocked at 10MHz (which obviously dosen't meet Nyquist criteria) will result in digital signal which frequency is 0.7MHz. That's an effect of double aliasing. First, the signal is mirrored around 5MHz (Nyquist frequency), which gives a signal of 10MHz-10.7MHz = -0.7MHz. It doesn't make any sense with single channel ADC (it does in quadrature system), so another aliasing occures mirroring the signal around 0Hz, and what You get is a signal having frequency of 0.7MHz.
This aliasing effect can be repeated as many times as input stage band width will allow. It is theoreticaly possible to sample a FM radio station using an ADC clocked at let's say 1MHz. However there are some things You should remember.
Odd number of aliases will result in reversed side bands. Increasing frequency of input signal will result in decrease of digital signal's frequency. This also implies reversed polarity of demodulated FM signal. Even number of aliases (like in example above) will result in normal side bands.
With single channel ADC it's not wise to have one of side bands partialy aliased (hovever it's perfectly OK in quadrature system).
ADC will sample everything, which is not filtered out, up to input stage bandwidth, with every possible aliasing effect.
It's getting harder to filter a band of desirable width while its center frequency increases (higher quality factor of a filter is required). The easiest way is to filter a signal at lowest possible frequency.
relations between bit rate max IF sampling and other values you can find in book "CMOS sample and hold circuits for high speed A/D conversion" Kok Chin Chang 1991
Could alias sampling truthfully track original signals?
I don't believe so.
But in datasheet for GP2015 and its series products, they use 5.714MHz to sample 4.309MHz signal and expect an almost idea output with 30% set high of the time.
As I simulate, with sampling frequency lower than 4 times of the signal frequency, there are some high bits lost. So how could the signal after samling still keep the 30% duty cycle before sampling?
Thanks!
You need to sample at twice the *bandwidth* of your desired signal. So if you had a 1MHz band centered at 4.309MHz, it would be theoretically possible to sample with a 2MHz clock.
!! I thought sampling time should be twice of the carrier frequency, for the Nyquist theory.
Is it the twice of the bandwidth the lowest frequency for subsampling?
thanks!