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a confusing question about MOS small signal model?

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byron

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For the MOS small signal model, there is Cgs between the gate and the source, is there any current flowing through this capacitor at small signal? in other words, is there any current flowing through the gate at small signal? Maybe it is a very stupid question, I am a little confused by it.
 

sutapanaki

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The current flowing in this capacitor is dependent on the operating frequency. Physically, you need to charge the gate channel capacitance in order to operate the transistor i.e. modulate its channel current. To charge this capacitance you need current. The higher the frequency, higher the current.
 

Humungus

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Furthermore, in deep submicron technologies you have to consider a non-negligeable DC current through the gate oxide due to tunnel effect. This tunnel current can be more or less disturbing to you depending on your application.
 

hqqh

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Hi byron,
as already said, there are capacitances in the small signal model of MOS devices, even at the gate (gate-source, gate-drain, gate-bulk). these capacitances consists of e.g. the gate-source overlap capacitance and the capcitance between the gate and the channel. and therefore these capacitances are dependend from the operating point of the MOS device.
greetings,
hqqh
 

byron

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so there is small signal current through the gate?
 

ET

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As they stated, it does flow current through the gate. You must wonder why Id=Is rather than Id+Ig=Is when applying small signal model. right?
 

linxf2003

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For current CMOS process, it is just a capacitor, so there is no real current. But for future process, it may be.
 

khouly

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in RF circuits there is a current flow through the gate capacitance and also there a serice resitance with the gate called non quasi static resitance and they have imprtance in the input impedance of the amplifiers in RF region
about 2 to 5 GHz
 

opamp741

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I think the question was not if there is Ig in SubMicron technology or in RF ckts , But the question is simply if there is any Ig we assume thru the MOS gate. Bcaz during pole zero and other analysis we often assume that there is capacitive loads like Cgs or Cgb at the gate but we never think of how this caps are going to be charged or dischange and we never take corresponding currents into account.
 

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