a basic question on differential amplifer

[Robertt]

When we calculate the maximum output swing, must we ensure every transisor in saturation region?

I did it letting the tail current all flow through one side circuit. But it seems wrong.

Thanks

 

[amarnath]

no,when one input of the diff amp becomes larger than the other input by a limit,then u will be turning off the other transsitor,this is because,the potential of the point which is taken as AC ground will rise and then since this is also the source potential of the other transsitor,u will be turning this transistor off when this source potential increases beyond a particular value. and thus,the output vout1 will be vdd and vout2 will be vdd-id*rd.

 

[AndrzejM]

When we calculate the maximum output swing, must we ensure every transisor in saturation region?

For DC yes, to be precise not "every" transistors but "upper" transistors are saturated and the "lower" are open circuit (or vice wersa, depending on + or - swing).

The output load and the frequency must also be taken into consideration!

 

[ezt]

Hi Robertt.
Do you know why we report a symmetric output swing? That's because, e.g. when we have a positive signal at one output end, there's a negative output on the other output end and both these outputs can be not larger than what makes devices cut off or do not act properly. So you must not test the output swing when almost all of tail current just flew from one side.

Regards,
EZT

 

[Robertt]

Hey,

Thank all of you. I asked this question because I couldn't understand one problem in Razavi's book.

The following is this circuit, calculate the maximum output voltage swing. Below this circuit is the answer from an e-version answer of all the problems in this book.

Now, I understand how to calculate Vout1,2(min), it's:

Vin,CM-Vthn

to ensure two input device remain saturated.

for Vout(max), I understand Vout(max)=Vdd-(|Vgs3|-|Vthp|)

What I cannot understand is that the answer use half Iss (ie. 0.5mA) to calculate Id3 as written in the fig.

Since we are calculating Vout(max), the currents flowing two sides must not equal. Then Id3 shouldn not equal to 0.5*Iss. I am really confused. Is the answer wrong?

 

[bamboo]

Hi Robertt,

You said you may understand
Vout1,2(min) = Vin,CM-Vth,n (Why use Vin,CM ?)
But you can't understand
Vout1,2(max) = Vdd - (|Vsg3|-|Vthp|)
When you use Vin,CM , Id =Iss/2 ?
Is it right? Why?

 

[amarnath]

this is because for a dc bias u are assuming that both transistors are in saturation,so the current gets divided equally between them,so u have a situation where Iss/2 FLOWS in both the branches.

regards
amarnath

 

[Robertt]

amarnath,

I am still lost here. Okay, let me put it in this way:

Say one side outputs the minimum voltage, if the other side outputs the maximum voltage?

In this case, if one side outputs Vin,CM-Vthn, if the other side must output Vdd-(|Vgs3|-|Vthp|)?


bamboo,

I think Vout(min)≈Vin,CM-Vthn is because input signal is rather small compared to Vin,CM. Say if Vin,CM=1.5V. Vin1-Vin2 maybe only 50mV. So Vout(min) roughly equal to Vin,CM-Vthn.

I don't know if my understand for this is correct. If I am not. please let me know what it is really going on here.

I am really disappointed by my poor foundation. Maybe I mixed up some basic concepts.

 

[bamboo]

Hi Robertt,
First, I think you point out one thing. A signal inculde DC part and ACpart. So you may divid an input signal into two parts : CM level and differential level.
When you design an OP , it's used to amp the small signal vary on the CM level. So when you calculate the parameter is based on this condition to keep the MOS on saturation region. In large signal part you will see Id1=Id2=Iss/2 (CM level)
If you use large (Vin1 -Vin2) as input , I think the ciruit is become comparator not OP. In this condition , I don't think the output swing will let you confuse.

 

[dog1357]

en, the maximum and minimum is referring to the differential output, so it is not like one node takes the maximum and the other node will have minumum, in fact, they do not occur at the same time.

I guess it is better to know how a single transistor woks in the saturation region, and how is the operation when a small AC signal is added into it. u may see the load line and Vgs-Ids curve, the interception are the opration points