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8bit full custom memory design

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kevin Park

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Before designing 512K memory design, I have a problem during design 8bit memory.
I am doing layout with Cadence Virtuoso. I had done layout 1bit cell first. And made 2bit cell with 2 instance of 1bit cell, 4bitcell with 2 2bitcell and 8bitcell with 2 4bitcell.
Finally, doing LVS with calibre(hierarchy), I had problem. It is that some transistor in 1bitcell is disapeared and moved to 8bitcell(top view).
Is there any reason the transistor in bottom level to move to top level hierarchy?

And in hierarchy design is it ok to intersect between two instance?
 

YESH_23

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caliber is not that efficient while showing the mistakes.

it is efficient in catching the mistakes

for example if u short a signal to vdd it will show an error as nets connected to vdd are wrong

it will not show the net shorted but the vdd ltself as an error

i think u got it

so cross check ur layout throughly

Added after 3 minutes:

while drawing layouts of such memory cells and all its better using virtuso xl

bcz its a schematic driven layout editor which simplifies the job

not that virtuso should not be used

depends.....
 

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