8bit Adder troubles simulating

Code Verilog - [expand]
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module full_adder(a,b,cin ,s ,C);
  
  input a, b, cin;
  output s, C;
  wire w1, w2, w3;
  
  and A1(w1, a, b), A2(w2, a, cin), A3(w3, b, cin);
  or O1(cout, w1, w2, w3);
  xor X1(s, a, b, cin);
endmodule
 
 
module adder(a ,b ,cin ,s ,status, C);
  input [7:0] a,b;
  input cin;
  output [7:0] s;
  output C;
  wire c1, c2, c3, c4, c5, c6, c7;
  output [3:0] status;
  
  full_adder add0(a[0],b[0],cin, s[0], c1);
  full_adder add1(a[1],b[1],c1, s[1], c2);
  full_adder add2(a[2],b[2],c2, s[2], c3);
  full_adder add3(a[3],b[3],c3, s[3], c4);
  full_adder add4(a[4],b[4],c4, s[4], c5);
  full_adder add5(a[5],b[5],c5, s[5], c6);
  full_adder add6(a[6],b[6],c6, s[6], c7);
  full_adder add7(a[7],b[7],c7, s[7], C);
 
  assign status[3] = c7 & C;
  nor zero(status[2], s[0], s[1], s[2], s[3], s[4], s[5], s[6], s[7]);
  assign status[1] = C;
  assign status[0] = s[7]&1;
endmodule
 
module testAdd(a, b, cin ,status,s, C);
 
input [7:0] a,b;
  input cin;
  output [7:0] s;
  output [3:0] status;
  output C;
  
  adder add0(a, b, cin, s, C, status);
endmodule

Code Verilog - [expand]
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// adder is defined with the following port ordering:
module adder(a ,b ,cin ,s ,status, C);
// you instantiate adder with the C and status swapped.
  adder add0(a, b, cin, s, C, status);
// you should always use named association to avoid the above problem.
  adder add0 (.a(a), .b(b), .cin(cin), .C(C), .status(status));

Code Verilog - [expand]
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// cout doesn't exist
  or O1(cout, w1, w2, w3);
// C does exist and is the carry out
  or O1(C, w1, w2, w3);