8 Bit by 16 Bit Multiplier (Verilog)

[heart]

Hi Everyone,

Can someone please help me on how to design a 8 by 16 Bit multiplier? Is it even possible? Thank you very much its very urgent for my project! Please help.
Should I convert the 16 bit input to 8 bit first using a multiplexer and then perform bit multiplication?
I would deeply appreciate your help.

Thank you

 

[permute]

c <= a*b;

if you're using Altera or Xilinx FPGA's, they both support this. you just need to make sure c has enough bits (eg 24b).

 

[heart]

No but this way is not going to be implementable in Spartan 3E FPGA.

 

[yadavvlsi]

Spartan 3 has inbuilt 18x18 multiplier. You can directly instantiate that using

MULT18X18 U_MULT18X18
(
.A () , // insert input signal #1
.B () , // insert input signal #2
.P () // insert output signal
);

For details see this application notes from xilinx.
https://www.xilinx.com/support/documentation/application_notes/xapp467.pdf