8-bit binary counter cant count down

[bhan1992]

i have an 8-bit up/down counter code as below, the problem is it wont count down. everytime i have a count down input, it just remain as the previous state.

Code:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity counter_code is
	port (
	output  :out std_logic_vector (7 downto 0);    
	up_down :in  std_logic;              
	clk     :in  std_logic;             
	reset   :in  std_logic         
			);
end counter_code;

architecture start of counter_code is
	signal count :std_logic_vector (7 downto 0);
	
	begin
		process (clk, reset, up_down)
		begin
		
			if (reset = '1' and rising_edge(clk)) then
			
				count <= (others=>'0');
				
			elsif (rising_edge(clk)) then -- rising edge
			
				if (up_down = '1') then
						count <= count + 1;
				elsif (up_down = '0' and count /= "00000000") then

						count <= count - 1;
				
				end if;
				

			end if;
			
		end process;
	output <= count;
end start;

waveform screenshot:

up_down = 0 'count down', = 1 'count up'

 

[BlackHelicopter]

What's up with your reset signal, thats not right.

 

[bhan1992]

i did not force any value into it thats y it is showing a red line

 

[BlackHelicopter]

i did not force any value into it thats y it is showing a red line

What happens if you do force it? I got your code to simulate fine.

You should also make some modifications to you code it's kind of confusing

something more like:

---

Code VHDL - [expand]
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process (clk, reset)
        begin
        
            if (reset = '1') then
            
                count <= (others=>'0');
                
            elsif (rising_edge(clk)) then -- rising edge
            
                if (up_down = '1') then
                
                        count <= count + 1;
                        
                elsif (up_down = '0' and count /= "00000000") then
 
                        count <= count - 1;
                
                end if;
                
 
            end if;
            
        end process;

---