8 bit ALU verilog codes are needed

[chooandmi]

Hi! I'm studying Electical Engineering. But It's hard for me. It's ashame that i coulnt catch up. I was given the hw to complete the 8 bit alu using modelsim with
adder , subtraction , multiplier, division option and 2bit select signal.
I've no idea how to start. Can you progamming wizard help help? The sooner is the better

 

[ramana459]

This is sample code.
but division operator symbol wont work in xilinx
for division you should write using algorithm only


module alu_code(clk,reset, a,b,out, sel);
input clk,reset;
input [7:0] a,b;
input [1:0] sel;
output [8:0]out;
reg [8:0]out;


always @(posedge clk)
if(reset)
out = 9'bX_xxxx_xxxx;
else
case(sel)
00: out = a + b;
01: out = a - b;
10: out = a * b;
11: out = a / b; //// this operator cannot work in xilinx
endcase

endmodule

 

[ljxpjpjljx]

ALU has different code version for different need!

 

[manish12]

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
------------------------------------------------------------
entity vhdl_alu is
port
(a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
sel : in std_logic_vector(3 downto 0);
cin : in std_logic;
y : out std_logic_vector(7 downto 0));
end vhdl_alu;
------------------------------------------------------------
architecture dataflow of vhdl_alu is
------------------------------------------------------------
signal arith : std_logic_vector (7 downto 0);
signal logic : std_logic_vector (7 downto 0);
------------------------------------------------------------
begin
------------------------------------------------------------
with sel(2 downto 0) select

arith <= a when "000" ,
a+1 when "001" ,
a-1 when "010" ,
b when "011" ,
b+1 when "100" ,
b-1 when "101" ,
a+b when "110" ,
a+b+cin when others;
------------------------------------------------------------
with sel(2 downto 0) select

logic <= not a when "000" ,
not b when "001" ,
a and b when "010" ,
a or b when "011" ,
a nand b when "100" ,
a nor b when "101" ,
a xor b when "110" ,
not(a xor b) when others;
------------------------------------------------------------
with sel (3) select
y <= arith when '0',
logic when others;
------------------------------------------------------------
end dataflow;


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