6800 clock signal :: delay time

[XC.6800]

6800 clock signal is defined to be NON OVERLAPPING phase-1 and phase-2

however reading from datasheet, the delay time "td" is maximum 9100 nano second.
this means phase-1 and phase-2 could be @ the same logic maximum 9100 ns.
which I find it is contradictory to the NON OVERLAPPING requirement.

could someone help me understand this confusion.

thank you very much
XC

 

[zorro]

Hi XC,

Non overlapping refers to H level.
Note that td has a minimum of 0 ns. So, logic H's can not overlap.
Regards

Z

 

[FvM]

this means phase-1 and phase-2 could be @ the same logic maximum 9100 ns

This conclusion is not founded by the datasheet. All specfications have to be kept at the same time. In this case, the tcyc specification implies, that only one of the two phase gaps can be extended to the maximum time amount of 9.1 µs.