65 nm Leakage Problem

[master_picengineer]

Hi all,
How to reduce the leakage effect in 65 nm devices ?
Thanks for your replies.

 

[research235]

use low power techniques like power gating ..

Suresh

 

[vak]

Use Multi VT libraries for your design to reduce the leakage power.

 

[master_picengineer]

Thank you all,
@ vak
Could someone explain what is Multi VT Libs and how they can help reducing the leakage ?

 

[rania_hassan]

AA,
you can use high Vth devices like I/O devices in some critical blocks like charge pump & MOS decoupling caps. but you will lose the speed.
the leakage is only concern when the MOS is off so test your power down mode & try to cut the leakage path by high Vth device in series with the low vth device
I hope I came to the point
best regards,
Rania

 

[onlymusic16]

Use MTCMOS technology

 

[master_picengineer]

Hi,
Can you onlymusic16 enumerate the avantages of this technology ?

 

[archillios]

hi,
you have some choice in 65nm era, such as coarse MTCMOS, Variable-Threshold CMOS, and traditional Multi-VT CMOS design techiques.

refer to this book in this forum:
"Low-Power CMOS__ Circuits[1][1]..Technology_ Logic Design and CAD Tools"
wish help~~~

 

[pratap_v]

Use multi vt libraries. Low vt cells can be used in the most critical paths and high vt cells for the positive slack paths.

 

[Vamsi Mocherla]

More importantly, the leakage (static) is dependent on the VGS on the gate and also the area of the device. So, design with a smaller area and a smaller VGS. In case you are using a transistor which takes logic 1 and logic 0, then use a higher VTH device. Speed as mentioned earlier is an issue.

Multi VT devices are found in every foundry for 65nm technology. Please look into the fab results for leakage and use the devices.

 

[sekapr]

multi-vt and power gating is the technique widely used

 

[onlymusic16]

Hi,
Can you onlymusic16 enumerate the avantages of this technology ?

Its multi threshold voltage cmos design technique.

 

[iwpia50s]

...and if you don't have a high VT library, lower the operating temperature.

 

[wjccentury]

Hi all,
How to reduce the leakage effect in 65 nm devices ?
Thanks for your replies.

Use multi-vt library, good power managerment scheme, and use floating prevent circuit between 2 different power domains, also power gating cell for power domain

 

[master_picengineer]

Hi,
Thank you all for your replies. You gave nice solutions.
@wjccentury
Could you elaborate what do you mean by power management Scheme and Floating prevent circuit ?
Thanks in advance.

 

[carna]

There is a book from Synopsys+ARM talking about this issue, its name is "LPPM"

 

[rain_181914]

I think you could try to add a nonsaliside block

 

[master_picengineer]

There is a book from Synopsys+ARM talking about this issue, its name is "LPPM"

Hi,
Thanks, please tell me the title of the book.
Could you share this book ?

Added after 56 minutes:

I think you could try to add a nonsaliside block

Hi,
Could you please elaborate. What do you mean by "nonsaliside block". Is there any paper discussing this technique ?

 

[Hards]

Please go through this doc

 

[hrushitha]

hi all,
discussions were good.
can anyone elaborate this
"More importantly, the leakage (static) is dependent on the VGS on the gate and also the area of the device. So, design with a smaller area and a smaller VGS. In case you are using a transistor which takes logic 1 and logic 0, then use a higher VTH device."

thanks