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Most modern FPGAs have high-performance carry look-ahead logic built into the logic cells. The synthesis tools will see the 64-bit add operator in your HDL, and automatically use the carry look-ahead logic. If you try to build your own adder and carry logic, you will get relatively poor performance.
For example, see "Figure 22 Carry Logic" in the "Spartan-3E FPGA Family Complete Data Sheet":
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