May 21, 2008 #1 F freewing Member level 1 Joined Mar 16, 2005 Messages 35 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,288 Activity points 1,592 500 mhz dac In 90nm CMOS, to design a 6-8 bit, 500MHz DAC, which topology gives smallest area? Currently, I'm thinking R-2R ladder, current steering, charge redistribution/algorithmic iterative DACs. Any thoughts on this? Thanks.
500 mhz dac In 90nm CMOS, to design a 6-8 bit, 500MHz DAC, which topology gives smallest area? Currently, I'm thinking R-2R ladder, current steering, charge redistribution/algorithmic iterative DACs. Any thoughts on this? Thanks.