freewing
Member level 1
500 mhz dac
In 90nm CMOS, to design a 6-8 bit, 500MHz DAC, which topology gives smallest area? Currently, I'm thinking R-2R ladder, current steering, charge redistribution/algorithmic iterative DACs. Any thoughts on this? Thanks.
In 90nm CMOS, to design a 6-8 bit, 500MHz DAC, which topology gives smallest area? Currently, I'm thinking R-2R ladder, current steering, charge redistribution/algorithmic iterative DACs. Any thoughts on this? Thanks.