5V voltage limiter for an FPGA board

[urousseau]

Hello,

I'm designing a FPGA Board with a +5V to +15V DC input specification. To be clear, we're using 5V and 12V wallplug with the same DC jack connector
From this input, I'm using DC/DC converter and LDO to create 1.1V, 1.5V, 1.8V, 2.5V and 3.3V.
But there is an issue regarding the onboard 5V generation: I'm expecting a way to limite the voltage power to 5V when using a 12V ACDC wallplug and to bypass it without any dropout when using 5V ACDC wallplug.
Can you help me?

 

[FvM]

5 volt limiter

Some LDO have an input capability of 20V and a few 100 mV droput only (e. g. LT1963 from Linear), they could be used as an easy and fully protected solution.

 

[urousseau]

voltage limiter 5v

Is it possible to use 2 LDO in // to get 3A output?

 

[FvM]

volt limiter 5v

You probably get an unequal and unstable current distribution, usually series resistors at the output are recommended when paralleling voltage regulators.

How about a LT1764 3A regulator? But the thermal handling capacity may be a problem.

For minimum power dissipation, a buck-converter with an additional controlled shunt switch would be probably a better solution. Unfortunately, most integrated buck-converters have a duty-cycle limitation due to MOSFET boost circuit at about 90 % on-time.