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50KHz phase cut rectifier has interval of erratic switching....why?

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treez

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Hello,

Please can you help solve the erratic switching that’s happening in my phase cut rectifier?

I have a 50KHz (sinusoidal) rectifier to which I have added phase cut circuitry, (to reduce the average output current)

Schematic………………………
https://i49.tinypic.com/34rucgj.jpg

Output current waveform with no phase cutting………….
https://i45.tinypic.com/kcl3z9.jpg


Output current waveform with phase cutting………….
https://i47.tinypic.com/14y3iw9.jpg

..how can I get rid of the bit where the waveform switches erratically near time = 70us?


[attached is a clearer schematic and the LTspice simulation file in .txt which can be converterd to .asc]
 

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  • 50KHz Phase cut rectifier.txt
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By design, the FET switches are shorting the input signal to the trigger circuit. I don't believe that the circuit can work without basic changes.
 
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Yes, though the FET switchs are only held on for as long as the monostable "tells" them to stay on.......then the FETs go back off and the trigger signal that you speak of is restored.

...if you run the simulation, you can see that it works...........

or were your comments only referring to the little bit near time = 70us?
 

The erratic switching is generated by a feedback from switch transistor to the lower trigger channel. It's a complex circuit with different interference pathes. I can't see how you conclude that the trigger should work without being disturbed by output switching. You say, it's working sometimes, but that's not enough, I suppose.

You didn't specify an intended duty cycle range, so it's effectively impossible to determine under which conditions the trigger circuit is working or not.
 
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Thanks, maybe i exaggerated the problem.................

https://i47.tinypic.com/14y3iw9.jpg

....the nasty erratic switching only happens 70us after start up...after this, the circuit operates beautifully (at least on the sim).

I was just wondering about how i can erradicate the erraticness at t=70us?

If i cant erradicate it, then i'll just live with it....but i have a terrible suspicion that the erraticness is a 'doom-monger', ...a 'grim reaper', waiting in the wings to destroy my circuit operation at some future date?

You say its complicated, but as you know, its just a comparator tripping a monostable which goes into a fet driver.....shorting the diodes with the fets diverts current away from the leds.

The duty cycle will likely be fixed on any individual product.........i am hoping for something like D=0.3 to D=0.85
 

I would expect a trigger circuit that's designed to give one pulse per halfwave, independent of output switching. By design, this isn't guaranteed anyhow.
 
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running the sim, i see what you mean......there are two trigger pules to the monostable for each FET-ON pulse...but this doesnt matter becasue the second one is caused by the first one, (as you say?) and the FETs are ON at that time anyway....so who cares if another pulse happens then.

It would be great if the simulation could be minorly adjusted to bring out the problem that you speak of....but i cannot bring out problems from listening to your posts.....though maybe i am interpreting your words incorrectly.

......running the simulation, after 70us, it works like a dream.....so i am loathe to strike the circuit so low..........my attitude toward this circuit is nowhere near as disfavouring as your own......i cannot understand how such a beatiful simulation operation is making you so doubtful as to this circuit?

My apologies FvM, i originally connected the "gate" to ground, but have now corrected this above.
 
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