[50 pts] Help for Passive component Layout

[mouzid]

Hi All,

I need to know how do layout for Resistors and capacitances. Can somebody help. The resistances wanted is between 10KΩ and 50 KΩ, the capacitance is between 200 fF and 20 pf.

I'm thinking of using the a Poly resistance and a Metal1 Metal 2 sandwich Capacitance. Am I on the right way ?

Please send to me material/tutorial on that issue.

All your suggestion, idea would be highly welcomed.

Please feel free to discuss with me that issue.

I 'll distribute 50 pts for those who helps.

Thanks in advance.

 

[fixrouter4400]

Hi mouzid - do you know what technology process are you using to do your layout?

To layout your resistor your need to know the poly resistivity...this way you can compute the number of squares to get the resistance value you need.


See the links hope this help

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[mouzid]

Thank you fixrouter4400 for your propt reply.

You're rigth. I forgot to say that I'm using the 65 nm process.
I'm using Cadence tool With eldo for layout and simulation.

Where can I find informations regarding the poly's resistivity ?

 

[k_90]

All of the information you require will be in the design rules supplied to you, set out by the fab. Normally these design rules advise you on the devices available(sp?) ie mim/poly caps resistors. These are normally supplied in a library which containe "pcells" otherwise you will have to draw them by hand(make your own pcells) , once you have one completed making others at various size wont take long.

 

[fixrouter4400]

Normally you can see the poly and metal resistivity in the process design rule(in text format or pdf) then you can search on that file about the electromigration etc.

And if you're using tsmc 65nm process the layout do come in design kit. All your component layout will be automatically done using VXL.

Also see this link for more info about resistor and capacitor layout.
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[manruru]

hello fixrouter...
these two links are so informative for start up people in resistor and capacitor.

cheers
manruru

 

[sat]

Which 65nm fab?
If TSMC - follow the device formation guide.
Also keep the layer usage doc handy.

I am curious - what application you will have in 65nm process that requires 50K res and a 20pf cap.
In case the requirement goes inside your ESD protection circuit, the R story will be entirely different.

Now, I will talk about some general stuffs
In general - poly is always doped & salicided/silicided to reduce overall sheet-res - un-silicided poly provides higher sheet-res. If you want to know what salicide is - google it. So, for TSMC process there is SAB layer [Salicide block] you are purposely blocking salicide to get deposited over resistor body region. Remember - the resistor terminal regions need to be over heavily implanted - you should have n-implant or p-implant on the terminal regions [n or p depends on poly is n or p type - p type offers even higher sheet res - as hole mobility is even lesser than electrons].
The shape of terminal regions - and additional contact resistors at the terminal needs to be taken into account - the terminal regions might be dog-bone shaped as well - provided the process allows dog-bone or not. If it is high value p-poly res - keep it over nwell [cold].

Regarding capacitor - for making high value capacitors - in general - either MOSCAP or MIMCAPs are chosen. Down 65nm as a gate leakage current is higher - MOSCAP is not recommended for large cap. Use MIMCAP.

Remember the parallel-plate capacitance formula - [dielectric-coeff * Area / distance].
Now, in the space between ordinary routable metal layers there are dielectrics - two types - ILD [intra-layer-dielectrics] and IMD [inter-metal-dielectrics] are purposely kept as low-K [K stands for relative dielectric-const of the material] and multi-layer to reduce effective dielectric-coeff - they also maintain substantial dielectric thickness between successive metal layers - so that parasitic capacitance between routed metals - and metal to substrate remains as low as possible. You should not think of making a canonical capacitor using successive metals.

MIM [Metal Insulator Metal] cap is a different beast altogether - foundries introduce another special metallization step for MIMCAP [they call it CBM or CTM based on placement] - and a very special high-K low-leakage dielectric is used in between a MIM layer and a routed metal layer - in between the high capacitor forms, only where there are MIM. They use same via - however as they are on the top of MIM - their height becomes different.