50% duty cycle and speed in a FPGA

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synq

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hi........

could any one help me to figure out the relation between 50% duty cycle and speed factor in FPGA.?

any links or documents.?

How far I need to keep the 50% duty cycle as Iam planning to boost the frequency from 20Mhz to 300Mhz.?
 

If you want to speed up your FPGA 15 times, DC is not your biggest problem.
 

There is no relation till you are using only one edge of clock. For both edges design the duty cycle exerts influence on timing requirements of logic which process data between opposite clock edges.

To achive 50/50 duty cycle of clock you can use DLL or DCM on Xilinx FPGAs.

Ace-X.
 

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