4046 FSK demodulation / loop filter design

[sh-eda]

Hi
I would really appreciate it if someone could help me. (Sort out some confusion )
I am intending to use the 74hc4046 to demodulate a FSK signal. The carrier centre frequency is around 165Khz and the deviation is around +/-2.5%. So I am using a frequency offset. (I am not using any frequency divider). The max signal frequency is around 4.8kHz baud, though it is more likely to 300baud eventually.
The problem I am having is understanding which phase comparator to use, the loop filter design i.e (The choice of zeta and settling time).
I have opted for PC2 at the moment, and a simple passive filter using a two resistor and cap. (R3/R4 and C2 from the datasheets).
I have been through the datasheets and the application notes.
In one of the datasheet it states that a "With a passive low-pass filter, the “4046A” forms a second-order loop PLL. So for a 2nd order low pass filter I think I should be using a zeta of 2. I have tried designing with these and the results component values don't look correct.

But it is my understanding that a passive filter will only be first order? If so I would choose a zeta of 0.7, from one of the graphs in the datasheet.
I wonder if someone could clarify this? Is this because of phase type of phase comparator adding a delay.
Some of information in the application sheets etc I have seen seems to agree (I will try to find this information again)

Thanks

 

[LvW]

sh-eda,

I am not sure if this answers one of your questions: Are you aware that signals of the PLL transfer function are not voltages but the PHASE?
That means: The VCO acting as an integrator regarding the phase and, thus, contributes the order n=1 to the overall transfer function.
That means: With a first-order loop filter the PLL order is n=2.

 

[sh-eda]

ok its sort of what I thought, yes it answers my question.
I've had a bit more time to play with the circuit now.
I'm trying to sort out which of phase comparator to use.
I'm getting the idea to use phase 1 which is just an xor, as it apparently less susceptible to noise which is important in my application,
The problem is I get a signal when the input frequency goes out of range. (i.e Below 1v or above the 4v on the VCO control pin), which doesn't happen using the phase comp 2.
I am wondering if there is a better way or way to get around this?
The only way I can this of is to increase the frequency range, but that would reduce the amount of signal I get out.