4-bit shift register using behavioral modelling

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pavani40444

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pls send me verilog code for 4-bit shift register using behavioral modelling
 

Please send your attempt first, and people will fix it.
 

Anyway lets help:

module shiftReg ( out, in, clk, reset);
input in;
input clk;
input reset;

output out;

reg [0:3] mem;

assign out = mem [3];

always @ (posedge clk)
begin
if (reset)
mem <= 4'b0;
else
mem <= {in,mem};
end

endmodule

Folks feel free to add comments.
 

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