Dec 22, 2012 #1 N naavid Newbie level 6 Joined Dec 22, 2012 Messages 11 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,348 4 bit ripple counter using four D flip flops without using other components. Can you please help.........
4 bit ripple counter using four D flip flops without using other components. Can you please help.........
Dec 23, 2012 #2 R rohitkhanna Banned Joined May 1, 2012 Messages 341 Helped 76 Reputation 150 Reaction score 75 Trophy points 1,308 Location New Delhi, India Activity points 0 Config each DFF as a divide by 2 - i.e. connect Q/ to D and input clock to CLK. Now connect them in series - Q1 - CLK2, Q2-CLK3, .... and so on. And there you are !! A 4 bit binary counter
Config each DFF as a divide by 2 - i.e. connect Q/ to D and input clock to CLK. Now connect them in series - Q1 - CLK2, Q2-CLK3, .... and so on. And there you are !! A 4 bit binary counter
Dec 23, 2012 #3 N naavid Newbie level 6 Joined Dec 22, 2012 Messages 11 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,348 Dear Rohit, Really thanks. It works.............................
Dec 24, 2012 #4 B babaduredi Member level 1 Joined Apr 28, 2011 Messages 39 Helped 9 Reputation 18 Reaction score 9 Trophy points 1,288 Location Bangalore Activity points 1,543 rohitkhanna said: Config each DFF as a divide by 2 - i.e. connect Q/ to D and input clock to CLK. Now connect them in series - Q1 - CLK2, Q2-CLK3, .... and so on. And there you are !! A 4 bit binary counter Click to expand... Hi Rohit, This way we will get asynchronous counter. Is it possible to make synchronous one using dff alone?
rohitkhanna said: Config each DFF as a divide by 2 - i.e. connect Q/ to D and input clock to CLK. Now connect them in series - Q1 - CLK2, Q2-CLK3, .... and so on. And there you are !! A 4 bit binary counter Click to expand... Hi Rohit, This way we will get asynchronous counter. Is it possible to make synchronous one using dff alone?
Dec 4, 2013 #5 R rids1 Newbie level 4 Joined Dec 4, 2013 Messages 6 Helped 1 Reputation 2 Reaction score 0 Trophy points 1 Activity points 33 module counterdff(clk,d0,d1,d2,q ); input clk,d0,d1,d2; output q; reg q0,q1; reg q; always@(posedge clk) begin if(clk==1) q0<=d0; if(q0<=1) q1<=d1; if(q1<=1) q<=d2; end endmodule i done it by same maanner bt my code is nt synthesizing...plz tell me error
module counterdff(clk,d0,d1,d2,q ); input clk,d0,d1,d2; output q; reg q0,q1; reg q; always@(posedge clk) begin if(clk==1) q0<=d0; if(q0<=1) q1<=d1; if(q1<=1) q<=d2; end endmodule i done it by same maanner bt my code is nt synthesizing...plz tell me error