4 Bit Flash ADC in 180nm Technology

[destro98]

I have designed a 4 bit flash ADC in cadence. I have used Two stage op amp as comparator and Fat tree TC to BC Encoder. I am attaching my Output image file .

I am getting some unnecessary zeros in my output. Can anyone help me about these drops and how to eliminate them? Thank You.

Fat Tree Encoder

 

[Dominik Przyborowski]

Your logic is asynchronous, so those zeros results from finite switching/propagation times of gates, I think.

 

[dick_freebird]

Not only finite (and unbalanced) switching times in
the logic, but comparator rising / falling delay
asymmetry can cause race conditions which turn
into output glitching. In the larger picture the
flash ADC data would be registered (nobody likes
to work with unstable data) and the trick is to
ensure that the strobe avoids the hazard regions.
This in turn probably wants a S/H or T/H front
end so that input data (analog) can be relied
upon. Making it no longer a real-time ADC in effect.

If you need "glitch free" output operation maybe
you want a self-timed output register that is
strobed on a code-change-detect, plus enough
lag to ride out the always-present glitching (but
this adds to delay and probably maximum conversion
rate).

 

[destro98]

Thanks for the reply. The spikes was due to my Logic gates and it is ok with me. I am having an issue with my ADC, it is not working as i want, i have attached the output graph, you can see in the graph that LSB and One bit in the output are not starting at low voltages. Is there any way to start the ADC at small voltages. Thank You.

 

[Dominik Przyborowski]

ICMR of your comparator doesn't cover input voltages below ~0.5V. You have to use rail-to-rail input stage.

 

[destro98]

I didn't get you. Could you explain or help with this rail to rail input stage?

 

[dick_freebird]

You could also use two styles of comparators, one that
has input range which includes ground but maybe not the
higher end, and another which includes the higher end
but not ground. These can be simpler and as long as they
give the right answer when they are "involved in the
decision" it's OK. Of course that wants checking. If
the output is registered then you might also look at
simple autozeroed capacitor-coupled comparators for
speed, simplicity and negligible drift attributes.

 

[destro98]

Thanks for the reply. I want mt ADC to operate from 0.3v to 3v, but my present config cannot operate below 0.5v. What can i do to achieve this?

 

[dick_freebird]

Are you talking signal, or supply?

 

[destro98]

I am using a Ramp input from 0 to 3.3 volts, Dc voltage as Vref and Power supply Vdd of 3.3 Volts and using current source of 60uA as Bias current.