4 bit counter based on pos edge of clock

[Drwut]

I'm trying to write a program which takes the pos edge of the clock and count how long it is in the high state for. Then, I need to send that number, the number of cycles, as an output. Here is my Module and TB. I keep getting an error saying my pulsewidth is an illegal inout or output port.
MODULE:
module Question2ASM ( input clock, reset, enable, highstate, output reg [3:0] pulsewidth);
initial begin
pulsewidth = 4'b0;
end
always @(posedge clock or enable or reset)
begin
if (reset || !enable)
pulsewidth = 4'b0;

else if (highstate)
begin
pulsewidth = pulsewidth + 1;
end
end
endmodule

TESTBENCH:
module Question2Testbench();
reg clock;
reg reset;
reg enable;
reg signal;

// set up clock for testbench
always
#1 clock = ~clock;

// initial values for input signal, reset signal, and enable signal
initial begin
signal = 0;
reset = 1;
enable = 0;


//table for randomly showing the count up value of pulsewidth
#5 enable = 1;
#1 reset = 0;
#1 signal = 1;
#5 signal = 0;
#3 signal = 1;
#8 signal = 0;
#10 signal = 1;
#5 signal = 0;
end

Question2ASM i0( clock, reset, enable, signal, pulsewidth);
endmodule




please help

# ** Error: (vsim-3053) C:/Users/Derek/Desktop/MODEL SIM FILES/Question2Testbench.v(31): Illegal output or inout port connection for "port 'pulsewidth'".
This is the error which comes up while I try to simulate it. I think it has an issue to do with it being assigned as a four bit register in the module, but the testbench wants to run it as a 1 bit.
Any help would be greatly appreciated.

 

[mail4idle2]

declare pulsewidth as 4 bit register