library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(txclk,grst:in std_logic;
cnt_out:out std_logic_vector(7 downto 0));
end counter;
architecture counter of counter is
signal cnt:std_logic_vector(7 downto 0);
begin
count:process(grst,txclk)
begin
if grst='1' then
cnt<="00000000";
elsif rising_edge(txclk) then
cnt <=cnt + "00000001";
end if;
end process;
cnt_out<=cnt;
end counter;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(txclk,grst:in std_logic;
cnt_out:out std_logic_vector(3 downto 0));
end counter;
architecture counter of counter is
signal cnt:std_logic_vector(3 downto 0);
begin
count:process(grst,txclk)
begin
if grst='1' then
cnt<="0000";
elsif rising_edge(txclk) then
cnt <=cnt + "0001";
end if;
end process;
cnt_out<=cnt;
end counter;
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?