can anyone explain me what happens in 4-8-16 beat transfer. i mean i have read the documents but i dont understand what happens in memory.
can someone explain how it take place with help if memory?
Hi:
At least there are some advantages:
1): From the AHB master / slave view, do you think which will improve the transfer bandwidth (or efficiency), compare with beat 1, beat 4, beat 8, beat 16 and incr transfer.(I mean if you need design an HAB master/slave and need make it as efficiency as possible.)
2): From the AHB arbiter view, do you think which will improve the transfer bandwidth (or efficiency), compare with beat 1, beat 4, beat 8, beat 16 and incr transfer.(I mean if you need design an HAB arbiter and need make it as efficiency as possible.)
3): For the memory view:
a): If your system memories are all on-chip SRAMs (simple SRAM, not cash), which will improve the memory access. I think beat 1 dangling between write/read (one cycle wirte then change to one cycle read) must be the lowest way.
b): If your system memories are on-chip cash, you must heared of cash line. It usually read in a cash line (maybe 4x32bits or 8x32 bits, but never 1x32bits).
c): If your AHB will access DDR memory on the PCB board, the shorter the burst length is, the less efficient the DDR access is. You can refer to the DDR memory DOC for help.
Thanks.