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4-8-16 beat transfer in ahb

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xpratx

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can anyone explain me what happens in 4-8-16 beat transfer. i mean i have read the documents but i dont understand what happens in memory.

can someone explain how it take place with help if memory? :oops:
 

yx.yang

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can anyone explain me what happens in 4-8-16 beat transfer. i mean i have read the documents but i dont understand what happens in memory.

can someone explain how it take place with help if memory? :oops:

Hi:
At least there are some advantages:
1): From the AHB master / slave view, do you think which will improve the transfer bandwidth (or efficiency), compare with beat 1, beat 4, beat 8, beat 16 and incr transfer.(I mean if you need design an HAB master/slave and need make it as efficiency as possible.)
2): From the AHB arbiter view, do you think which will improve the transfer bandwidth (or efficiency), compare with beat 1, beat 4, beat 8, beat 16 and incr transfer.(I mean if you need design an HAB arbiter and need make it as efficiency as possible.)
3): For the memory view:
a): If your system memories are all on-chip SRAMs (simple SRAM, not cash), which will improve the memory access. I think beat 1 dangling between write/read (one cycle wirte then change to one cycle read) must be the lowest way.
b): If your system memories are on-chip cash, you must heared of cash line. It usually read in a cash line (maybe 4x32bits or 8x32 bits, but never 1x32bits).
c): If your AHB will access DDR memory on the PCB board, the shorter the burst length is, the less efficient the DDR access is. You can refer to the DDR memory DOC for help.

Thanks.
 
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thanks man for the reply.
really appreciated.

but my confusion is really basic. how are HSIZE and HBURST related?
if i try to send 8 bit wrapping from a memory interfaced with master what will happen??
 

yx.yang

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thanks man for the reply.
really appreciated.

but my confusion is really basic. how are HSIZE and HBURST related?
if i try to send 8 bit wrapping from a memory interfaced with master what will happen??

HSIZE refer to the bit width of your each beat transfer and HBURST refer to the number of beat you want to trans for one request.
While we usually make the whole bus share the same bit width. For example the whole AHB bus is 32 bits or 16 bits.
Of cause you can make the AHB bus 32 bits, while just use HSIZE == 16 bits. What advantage do you see from this transfer?
I just see dis-advantage of that:
1): Make the slave that need recieve such request more hard to design.
2): Lower the efficient of AHB bus transfer.

Note: the simpler you design is, more stable and less bug will be in your design and you will be more happy.
 

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ok i get it.

but if hsize is 256 bits and our bus width is 32 bits then we have to divide our transfer to 8 blocks for one beat.is that right??

also according to arm document i assume when it talks about transfer it has a 8 bit wide memory. is it true??
 

yx.yang

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ok i get it.

but if hsize is 256 bits and our bus width is 32 bits then we have to divide our transfer to 8 blocks for one beat.is that right??

also according to arm document i assume when it talks about transfer it has a 8 bit wide memory. is it true??

For "hsize is 256 bits and our bus width is 32 bits": at this case, the maximal hsize value will be 32bits, you can't use hsize related to width such as 64, 128, 256. While you do can use hsize related to width 8,16,32. That's to say: hsize refer to the bit width of data you transfered on the AHB bus for each beat (or each clock cycle), so hsize can't bigger than the physical AHB bus width.

For "arm document i assume when it talks about transfer it has a 8 bit wide memory": You'd better read the DOC carefully. To my understaing, for ARM7 and ARM9 serise CPU cores, it usually has 32 bits data width. While memory is out of ARM core. So you can choose any bit width memory. While for system efficient consideration, designer usually use memory width equal or bigger than the CPU data bus width.

Thanks
 
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