3D-Array Port (natural range <>)

[vollbr0t]

Hi,

i would like to create a module (A) with a 3d-array port. To create an array-port i have to use a packge to declare the type of array. I do this like this:

TYPE test_type is array (natural range <>, natural range <>, natural range <>) of std_logic;

I have to use "natural range <>" for all three dimensions because the portwidth is depending on generics passed to A:

entity A is
generic(
gen_1 : natural := 5,
gen_2 : natural := 6,
gen_3 : natural := 7);
port(
matrix : IN test_type(gen_1 downto 0, gen_2 downto 0, gen_3 downto 0) );

The simulation works fine with this, but in synthesis i get "Matrix not supported yet" on the 3D-Port-Line.

Because of the required "natural range <>" i can not use subtype for the declaration in the package, and passing the generics to the package to not use natural range is not possible.

Do you have any idea of getting this to syenthesis?

Best regards,
Jan

 

[TrickyDicky]

The only answer is to use another synthesisor. multi-dimensional arrays are not used very often and some synthesisors may not support them. Why synthesisor and what version are you using?

But my question is why have you made a 3d matrix of std_logic? why havent you made a 2d matrix of std_logic_vector?

 

[vollbr0t]

i don not think that its possible to declare something like this:

TYPE test_type is array (natural range <>, natural range <>) of
std_logic_vector(natural range <>);



*edit
I'm using ISE 13.2

 

[TrickyDicky]

1. you have to set the length of the std_logic_vector when you declare it, so it would have to be:

type test_type is array(natural range <>, natural range <>) of std_logic_vector(7 downto 0);

unless you can find a VHDL 2008 compatible synthesisor, where you can leave the std_logic_vector as natural range <>.

I would avoid declaring arrays of std_logic - it makes life a little annoying.

2. I dont use ISE, but I know quartus (altera) would probably support it. Xilinx is renowned for being a bit slow to catch up with everyone else!

 

[vollbr0t]

but this is the problem: all three dimensions have to be generic!

 

[permute]

you may have to make a soft-type. eg:
std_logic_vector(M*N*P-1 downto 0);
and then perform the indexing to get specific items.