Help on Verilog code

[kevindog]

Verilog code about pulse generation

I am new to Verilog. Working on a project involving in pulse generation using verilog. Could someone else help me go through this code I got from web?

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module pulse_gen
 (
   input        Trigger,
   output       Pulse_Out,
   input [31:0] Pulse_Width,
   input        Clock
 );
   
reg [1:0] trig;
 
always @(posedge Clock)
 trig <= {trig[0],Trigger};
 
wire ld_cnt = (trig == 2'b01) ? 1'b1 : 1'b0;
 
reg [32:0] cnt;
 
always @(posedge Clock)
  if      ( ld_cnt )   cnt <= {1'b1,Pulse_Width};
  else if ( !cnt[32] ) cnt <= cnt;
  else                 cnt <= cnt - 1'b1;
  
assign Pulse_Out = cnt[32];
 
endmodule

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Another question is that this code generate a single pulse based on a trigger, if it's possible to generate a series of same pulse, like 5 same pulse sequence?

Thanks a lot in advance!

 

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Re: Verilog code about pulse generation

I am new to Verilog. Working on a project involving in pulse generation using verilog. Could someone else help me go through this code I got from web?

That isn't a question, what exactly is the problem with understanding the code. Or are you expecting a line by line description of everything in the code (sorry not going to happen)? If you don't know the syntax then learn that first with the numerous tutorials on the web.

Another question is that this code generate a single pulse based on a trigger, if it's possible to generate a series of same pulse, like 5 same pulse sequence?

Sure it can be changed, if you know what kind of circuit you want to do this, like if you want a counter to space them out if you want to control it by an FSM or something else entirely. That is where the design comes into engineering.

 

[kevindog]

Re: Verilog code about pulse generation

That isn't a question, what exactly is the problem with understanding the code. Or are you expecting a line by line description of everything in the code (sorry not going to happen)? If you don't know the syntax then learn that first with the numerous tutorials on the web.


Sure it can be changed, if you know what kind of circuit you want to do this, like if you want a counter to space them out if you want to control it by an FSM or something else entirely. That is where the design comes into engineering.

Thanks for your comments. I am working on the tutorials.

I have a FPGA development kit with SPARTAN-6 in it. In this case, which way that you mentioned will be the easiest for a new bee?

Thanks a lot!

 

[dpaul]

I have a FPGA development kit with SPARTAN-6 in it. In this case, which way that you mentioned will be the easiest for a new bee?

FPGA is the target implementation of your Verilog code/design.
You still haven't clearly mentioned what you want do.

Another question is that this code generate a single pulse based on a trigger, if it's possible to generate a series of same pulse, like 5 same pulse sequence?

Speculating: There is of course clock. If there is an input pulse, then there will be 5 output pulses each of the same pulse-width and equally spaced. Is this the function you want to implement?

 

[kevindog]

FPGA is the target implementation of your Verilog code/design.
You still haven't clearly mentioned what you want do.


Speculating: There is of course clock. If there is an input pulse, then there will be 5 output pulses each of the same pulse-width and equally spaced. Is this the function you want to implement?

There is a trigger as an input pulse, this trigger is from a PC command, using FPGAlink library. The function I am looking for is generating 5 equally spaced output pulses when there is an input pulse received.

Thanks you!

 

[dpaul]

I hope you understand that the min pulse width will be equal 1 clock cycle and the min time between two pulses is also equal to 1 clock cycle. You need to enable a counter to start counting up through the input trigger signal. Since you need to generate 5 pulses so let your counter count upto 10. On every even count value (2, 4,6, 8,10) drive a signal high which would be your 5 o/p pulses.

 

[kevindog]

I hope you understand that the min pulse width will be equal 1 clock cycle and the min time between two pulses is also equal to 1 clock cycle. You need to enable a counter to start counting up through the input trigger signal. Since you need to generate 5 pulses so let your counter count upto 10. On every even count value (2, 4,6, 8,10) drive a signal high which would be your 5 o/p pulses.

Thanks a lot dpaul!
I understood the logic that you described and it is helpful. As I am new to verilog, I actually don't know how to implement it. Can you point me some learning materials specific to this topic online? Do you think some modification to this code will be okay or I have to start something completely different?

Another question, is there a easy way to define width for generated pulses?

Thanks again!

 

[kevindog]

I was able to generate one pulse when the trigger is high based on the code. The code did everything and I only nested it in my module.

The following question I have is how can I repeat this pulse by 5 times?

Any input will be appreciated!
Thanks!

 

[dpaul]

Can you point me some learning materials specific to this topic online?

Online help is there to clear your fundamentals. Customization is your own task. It is pretty simple, do you know how to implement counters?

Step1 - Inside one always block you start incrementing a counter once your input pulse is sensed high by the clock. A 4 bit counter in enough. Simulate and check your design.
Step2 - In another always block just drive a single bit output high on specific values of the count register. Use either if-elseif-else or case statements.
Your work is done!

Rewrite a clean code.

always @(posedge Clock)
 trig <= {trig[0],Trigger};

trig[0] value is unknown, it is not initialized, so it would likely propagate X, don't do such things.

I was able to generate one pulse when the trigger is high based on the code. The code did everything and I only nested it in my module.
The following question I have is how can I repeat this pulse by 5 times?

It is not a good way of implementation. Try not to think of HDL coding as software coding.

If you break the steps as I have told above, you can easily implement it.

 

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How about an FSM implementation where the pulse width, pulse spacing, and number of repetitions are all programmable.


Things like the cntr clearing, trig synchronization (if needed) are left to the OP to figure out.

- - - Updated - - -

And the counter version if you only want the pulses to be 1 clock cycle wide and spaced 1 clock cycle apart would be easy....

The counter would have to do the following counting sequence (0-9-0) and the Pulse output is the LSB of the counter.

000 0 // no trigger
000 0 // trigger
000 1 //  so start counting.
001 0
001 1
010 0
010 1
011 0
011 1
100 0
100 1 // fifth output pulse
000 0 // clear the counter

I won't write the code for this as it's just a counter and you are trying to learn how to design with Verilog.