I did a TSMC .18u cell library specific design instantiating most of the components from the library. it took around a month to design/verify/synthesize. it was a combination of radix4/wallace tree multipliers.
to design with gates is not that hard. c that link i gave you.. if u r not worried abt max freq.. then u can go for radix 4 booth muliplier.
Thanks for your useful link.
My teacher required me that the multiplier must output the product after two clock cycles. So I think i can not use the booth encode modeling or the sequential shift and accumulation modeling. Maybe the only modeling i can use is the cobinational shift and accumulation modeling.
Thanks for your useful link.
My teacher required me that the multiplier must output the product after two clock cycles. So I think i can not use the booth encode modeling or the sequential shift and accumulation modeling. Maybe the only modeling i can use is the cobinational shift and accumulation modeling.
Output after 2 clock cycle means 2 stage pipelined design. just put a register before the final rounding operation. or during the addition of partial products generated by the booth encoder..