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3-to-6 decoder task problem- behaviour definition, diagram

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funjoke

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help with 3-to-6 decoder

a 3-to 6 binary decoder has an enable signal.When disabled or invalid code is applied to the decoder ,the decoder will output zeros.When enabled,input codes from 000 to 101 are decoded.Draw the block diagram of 3-to-6 decoder and define its behaviour using a truth table.

may i know how to do this question ?

Re: help with 3-to-6 decoder

Looks like your homework question. Did you gave it a try?
Let us know how far did you reach, we can help you out then.
You will not learn anything from ready solutions.

funjoke

Points: 2
help with 3-to-6 decoder

this is pass year question.and i just know how to do 2-to-4 decoder.this one i really dunno

Re: help with 3-to-6 decoder

Ok. Here is the solution.
C(MSB), B, A(LSB) are the three select inputs.
ENABLE is Active high.
Outputs are all active high.
Last two input codes 110 and 111 are invalid inputs which produces 0 on all outputs.
Code:
+-------------+
| Truth Table |
+-------------+
+-------------------------------------------------------------------------------------+
| C        B        A     ENABLE      Q0       Q1       Q2       Q3       Q4       Q5 |
+-------------------------------------------------------------------------------------+
| X        X        X        0        0        0        0        0        0        0  |
| 0        0        0        1        1        0        0        0        0        0  |
| 0        0        1        1        0        1        0        0        0        0  |
| 0        1        0        1        0        0        1        0        0        0  |
| 0        1        1        1        0        0        0        1        0        0  |
| 1        0        0        1        0        0        0        0        1        0  |
| 1        0        1        1        0        0        0        0        0        1  |
| 1        1        0        1        0        0        0        0        0        0  |
| 1        1        1        1        0        0        0        0        0        0  |
+-------------------------------------------------------------------------------------+

Re: help with 3-to-6 decoder

what is the module definition of the 3-to-6 decoder?

Added after 1 minutes:

the block diagram is like that ?
this is the circuit i think

Added after 27 seconds:

the block diagram is like that ?
this is the circuit i think

Re: help with 3-to-6 decoder

What i showed above is the actual circuit using NOT and AND gates.
If Verilog module is what you are asking for, here it is
Code:
// 3-to-6 decoder with an active-high enable (E)
// and active-high outputs (C is msb and A is lsb)

module _3_to_6_decoder(C, B, A, E, Y);
input C, B, A, E;
output [0:5] Y;
reg [0:5] Y;

always @(C or B or A or E) begin
if (E == 1)
case ({C,B,A})
3'b000:   Y = 6'b000001;
3'b001:   Y = 6'b000010;
3'b010:   Y = 6'b000100;
3'b011:   Y = 6'b001000;
3'b100:   Y = 6'b010000;
3'b101:   Y = 6'b100000;
default:  Y = 6'b000000;
endcase
else Y = 6'b000000;
end
endmodule

Re: help with 3-to-6 decoder

write if only to describe 3- to-6 decoder

here i attached the answer for it and can help me checked and correct it if there is any error

(output reg[5:0] op_y,
input [2:0] ip_a,
input ip_en);
//*****************************
always@(ip_en,ip_a)begin
if(ip_en == 2'b1)begin
if(ip_a == 3'b000)op_y=6'b000001;
else if(ip_a == 3'b001)op_y=6'b000010;
else if(ip_a == 3'b010)op_y=6'b000100;
else if(ip_a == 3'b011)op_y=6'b001000;
else if(ip_a == 3'b100)op_y=6'b010000;
else if(ip_a == 3'b101)op_y=6'b100000;
else if(ip_a == 3'b110)op_y=6'b000000;
else if(ip_a == 3'b111)op_y=6'b000000;
else op_y=6'bx;
end

else if(ip_en ==2'b0)
op_y=6'b000000;

else
op_y=6'bx;
end
/*

Re: help with 3-to-6 decoder

Since ip_en is 1 bit you should use 1'b1 and 1'b0 instead of 2'b1 and 2'b0.
Why do you tri-state outputs when input is invalid? The question said outputs should be 0.

Here is the optimized version
Code:
(output reg[5:0] op_y,
input [2:0] ip_a,
input ip_en);
//*****************************
always@(ip_en,ip_a)begin
if(ip_en == 1'b1)begin
if(ip_a == 3'b000)op_y=6'b000001;
else if(ip_a == 3'b001)op_y=6'b000010;
else if(ip_a == 3'b010)op_y=6'b000100;
else if(ip_a == 3'b011)op_y=6'b001000;
else if(ip_a == 3'b100)op_y=6'b010000;
else if(ip_a == 3'b101)op_y=6'b100000;
else op_y=6'b000000;
end
else
op_y=6'b000000;
end

Re: help with 3-to-6 decoder

but just now you gave that code is which part

now got 2 part for this question
a)module definition
b)use case only to describe it

Re: help with 3-to-6 decoder

funjoke said:
but just now you gave that code is which part

now got 2 part for this question
a)module definition
b)use case only to describe it
I am sorry I don't understand your question. Can you please re-phrase it?

Re: help with 3-to-6 decoder

mmm, this post has been already too long for a pass year question.....

Re: help with 3-to-6 decoder

daviddlc said:
mmm, this post has been already too long for a pass year question.....
I know right !! :wink:

Re: help with 3-to-6 decoder

// 3-to-6 decoder with an active-high enable (E)
// and active-high outputs (C is msb and A is lsb)

module _3_to_6_decoder(C, B, A, E, Y);
input C, B, A, E;
output [0:5] Y;
reg [0:5] Y;

always @(C or B or A or E) begin
if (E == 1)
case ({C,B,A})
3'b000: Y = 6'b000001;
3'b001: Y = 6'b000010;
3'b010: Y = 6'b000100;
3'b011: Y = 6'b001000;
3'b100: Y = 6'b010000;
3'b101: Y = 6'b100000;
default: Y = 6'b000000;
endcase
else Y = 6'b000000;
end
endmodule

i mean this one is module definition or using case to describe ?

Re: help with 3-to-6 decoder

If I get it right what you are asking. Both the module definitions will work.
You can either user "if-else" or "case". Your choice.

Re: help with 3-to-6 decoder

by the way what is mean by module definition ?>

Re: help with 3-to-6 decoder

can anyone explain with me what is the module definition ?

Re: help with 3-to-6 decoder

Looks like you are not very familiar with Hardware Description Language.
Read Verilog / VHDL tutorials.
A module is nothing but a circuit meant to perform a certain logical operation.

Re: 3-to-6 decoder task problem- behaviour definition, diagr

if using for to describe it ,

here is my answer

integer i_position;

always@(ip_a,ip_en)begin
if(ip_en==1'b0)
op_y=6'b000000;
else if(ip_en==1'b1)begin
for(i_position=0;i_position<6; i_position=i_position+1)
if(ip_a==i_position)
op_y[i_position]=1'b1;
else if(ip_a!=i_position)
op_y[i_position]=1'b0;
else
op_y=6'b000000;
end
else
op_y=6'b000000;
end
end module

can help me check correct a not ,thanks

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