3 order loop filter in PLL

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Hi all :

I'm a newb of PLL designer. I have read materials about how to design 3rd order loop filter.

[the schematic just like : (C1// R2+C2) shunt to gnd with additional pole (R3,C3)]

But here comes the rules : R3>2*R2 ; C3<0.1*C1

why here comes this rules?

I have read about several paper but none of them gives the reason

Can anyone answer me ? Please.
 

1 st order are inherently stable but noisy
2nd order are less noisy and C2/C1 ratio affects pole position
3rd order are inherently unstable with >180 deg phase shift and negative feedback becomes positive feedback.

Rule of Thumb ratios help provide LPF additional rolloff using lag-lead filters to give phase margin at unity gain and may have less jitter.
 

Thanks, SunnySkyguy.

So, if I design the additional pole carefully , and the additional pole does not degrade phase margin very much
it is alright even I don't follow the rule ?
(i.e. R3 < R2 ; C3 = C1)
 

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