3 bit counter with reset

[sanjanavee]

Hey this is my vhdl program for a 3 bit counter with reset.. now i need to know how i can use another 3 bit counter simultaneously in such a way that while the 1st counter is resetting the 2nd counter counts and while the 2nd counter is resetting the 1st counter counts. This is done in such a manner that any bits received even during the reset time is counted by either of the counters.. without leaving out any bits.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity BinCount3bit is
port(
clk : in std_logic;
reset : in std_logic;
sel : in std_logic;
q : out std_logic_vector(2 downto 0)
end BinCount3bit;

architecture behavioral of BinCount3bit is
begin

process(clk,reset)
begin
if reset = '1' then
q <= (others => '0');
elsif(rising_edge(clk))then
if sel = '0' then
q <= q+1;
else
q <= q+2;
end if;
end if;
end process;

end behavioral;

 

[amitjagtap]

process(clk,reset)
begin
if reset = '1' then
q <= (others => '0');
elsif(rising_edge(clk))then
if sel = '0' then
q <= q+1;
else
q <= q+2;
end if;
end if;
end process;

Why q<=q+2 is used....It doesn't make any sense... else part is not required in your code...OR apply high impedance when sel='1'.
About your question...I think you need two loadable counters...so that if one counter is counting and reset occurs...then second counter should start counting....
HOpe i understood correct...

 

[sanjanavee]

Why q<=q+2 is used....It doesn't make any sense... else part is not required in your code...OR apply high impedance when sel='1'.
About your question...I think you need two loadable counters...so that if one counter is counting and reset occurs...then second counter should start counting....
HOpe i understood correct...

yes exactly.. I need to make sure that no bits are lost during the reset of 1 counter.. so im using another counter.
but how exactly do i execute this vhdl?

 

[imbichie]

This you can make by negating the reset of 1st counter and mapped to the reset of the 2nd counter. So when the 1st counter is out of reset then the 2nd counter will be in reset mode, and when the 1st counter is in reset mode then it will make the 2nd counter out of reset

 

[rajavel.rv]

Hey this is my vhdl program for a 3 bit counter with reset.. now i need to know how i can use another 3 bit counter simultaneously in such a way that while the 1st counter is resetting the 2nd counter counts and while the 2nd counter is resetting the 1st counter counts. This is done in such a manner that any bits received even during the reset time is counted by either of the counters.. without leaving out any bits.

entity BinCount3bit is
port(
clk : in std_logic;
reset : in std_logic;
sel : in std_logic;
q : out std_logic_vector(2 downto 0)
end BinCount3bit;

architecture behavioral of BinCount3bit is
begin

process(clk,reset)
begin
if reset = '1' then
q <= (others => '0');
elsif(rising_edge(clk))then
if sel = '0' then
q <= q+1;
else
q <= q+2;
end if;
end if;
end process;

end behavioral;

Hi... This is Raja.. I think u r using a counter 3 bit.. Its having only 2^3 = 8 possible outputs (000,001....111). If 1st counter is reset means 2nd counter is automatically switched on and 2nd counter reset means 1st counter is switch on.. its a countinously looping concept.. if the 1st counter reset means we nead a reset value for the 1st counter. if am taken 111 is the reset value of the first counter and written the coding below...

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity bitcount3 is
port(
clk : in std_logic;
reset : in std_logic;
q0 : out std_logic_vector(2 downto 0);
q1 : out std_logic_vector(2 downto 0));
end;

architecture rtl of bitcount3 is

signal cnt1 : std_logic_vector(2 downto 0);
signal d : std_logic;

begin

q0 <= cnt1 when d ='0' else (others=>'0');
q1 <= cnt1 when d ='1' else (others=>'0');

process(clk,reset)
begin
if reset = '0' then
cnt1 <= (others=>'0');
d <= '0';

elsif clk='1' and clk'event then

cnt1 <= cnt1 + "1";
if cnt1 = "111" then
d <= not d;
end if;

end if;
end process;
end;