scanning flip flops with reset pins

[kichhu]

I read this in a book
"Some flip-flops can not be made scannable like reset pins, clock gated flip flops"

Wondering if it means flip-flops with reset pins or flip-flops carrying reset pins of an other flip-flop...and why are they non scannable

Thanks

 

[krishna2728]

**broken link removed**
**broken link removed**

 

[kichhu]

Hi
Thanks for the links....read through them
Sorry if I didnt get my question clear...

"I was wondering y is that flip-flops with reset pins not scannable"

Thanks

 

[yadavvlsi]

The purpose of scan is to test the chip after fabrication. This can be done only by controlling primary inputs of the chip and observing at primary outputs of the chip. First test vectors are applied at primary input and shifted to primary output using scan flops. There are two thing that determines the testability of chip, these are controllability and observability means you should be able to control a node inside using primary inputs and observe at primary output. Now the flip-flop with reset are difficult to control. because if reset get activated its output will be zero and you have no control from primary inputs.

Design for testing - Wikipedia, the free encyclopedia

 

[jducluzeau]

Kicchu,
There is no problem to insert scan on flip flop with reset pins. You just need to control your reset path that's why no flip flop on reset path must be scanable.
What your books want to say, you don't have scan flip flop which control synchronized reset or clock gating.
For example, for a simple stuck at fault test, there are three steps :
1- shift-in :Each input scanable Flip Flop is set in a state through the different scan chain.
2 - capture : Flip flop captures their input.
3 - shift out : you can obsereve the result

If a flip flop which controls a reset is in a scan chain,the reset is asserted during the second step. Then some scanable flip flop can be reset and they don't capture their input but set their ouput to zero.


This is the same for clock gating. Imagine a flop which enable a clock gating, it means capture is not possible for certain flops.

 

[pavanhs]

Hi

So does this Scan also dependent on Clock Frequency???
If so scan should be run in less frequencies or High Frequencies??

 

[rca]

If you synthesyze your design for a certain clock frequency, I don't know how you could garantue the scan to work as a higher frequency.
And the second point, do you have the IO pad which could work at the same frequency as the internal clock system? if no you need to reduce your scan clock frequency.

 

[pavanhs]

Thanks for the Reply,

Ya i Have my IO Pads which allow only Lower frequencies.
But Why IO Pads will have a limitations like to run at only Lower frequencies.

Thanks in Advance
Pavan HS

 

[rca]

The capacitance at the pad could be huge compare to the capacitance inside the design. The testing machine could add 100pF.