physical design fixing violations

[pavithra226]

how to fix maximum capacitance violation, max transition violation using cadence encounter

 

[yadavvlsi]

optDesign -preCTS -drv

Replace -preCTS with the stage you are fixing DRVs.

 

[pavithra226]

how to fix fanout violations?
i already did seOptMode -fixFanoutLoad true
fallowed by optDesign -preCTS. so how to fix the violations manually?
What is the difference between preCTS, CTS, postCTS & postCTS_hold steps?

 

[pavithra226]

What is Antenna effect , cross talk, IR drop, Multicut via, multicut metal.mincut via & mincut metal mean?

 

[yadavvlsi]

Check these links:
https://groups.google.com/forum/?hl=en#!topic/vlsi-design-forum/6RQWVTQ_Sh0
https://www.edaboard.com/threads/217088/#2
https://groups.google.com/forum/?hl=en#!topic/vlsi-design-forum/iHKBKodYQ2U
https://www.edaboard.com/threads/201441/#2

 

[pavithra226]

how to fix geometry violations such as shorts,wiring & sameNet erorrs?

 

[yadavvlsi]

# Delete the nets having DRC violations
editDeleteViolations
#Reroute deleted nets
ecoRoute

You can try this multiple times.

 

[pavithra226]

@yadav: am getting these viloations at the sign-off stage affter adding bufers to componsate transViolation. So, does deleting these nets causes deleting any of those buffers added?

Also how to fix SI(signal integration) errors?

 

[yadavvlsi]

@yadav: am getting these viloations at the sign-off stage affter adding bufers to componsate transViolation. So, does deleting these nets causes deleting any of those buffers added?

Also how to fix SI(signal integration) errors?

No, It will only delete the nets which have DRC violations. For SI fixing you can use optDesign -postRoute -si

 

[pavithra226]

thanx yadav
At the sign-off stage how to overcome denity violations?
i tried editFixWidewires but it dint help much.
Can you please suggest any solution?

 

[rca]

Why do you want to clear the fanout violations?
These violations did not involve in timing liberty table.

 

[pavithra226]

Why do you want to clear the fanout violations?
These violations did not involve in timing liberty table.

i want to clear density violation not fanout

 

[yadavvlsi]

editFixWidewires splits wires that violate the MAXWIDTH value in the LEF LAYER (Routing) statement. Also splits diagonal wires whose width is greater than the MAXWIDTH value as they are drawn. It doesn't fix density violations. For density violation metal fill is done.
https://www.cadence.com/rl/Resources/conference_papers/4.2Paper.pdf

 

[pavithra226]

after this am getting min area & min step errors how to go about that?

 

[pavithra226]

# Delete the nets having DRC violations
editDeleteViolations
#Reroute deleted nets
ecoRoute

You can try this multiple times.

actually this wont help much, If u again check for DRC the violations appear as it is

 

[pavithra226]

Why do we get Min-step violations at the sign-off stage?
What is its significaence?

 

[pavithra226]

How to ovecome the DRC related to Metal & via.
How to control the routing layers & vias?

 

[pavithra226]

i am working with soc -encounter. while routing the no violations were reported.
but when verified with calibre -lvs its showing 4 incomplete nets. when checked for same nets in soc - E those are no connected as required.
what would be the reason & how to overcome such violations.