zero cycle path in FPGA

[Guru59]

hello all,

In one my ASIC designs we have a zero cycle path.
How do we make sure this in FPGA prototyping.

thanks

 

[yadavvlsi]

A zero cycle path is a timing path that propagates from one flop to another racing the propagation of the same clock edge. This is a race condition. The RTL code must be modified to remove all zero cycle timing paths.

WHY: Zero cycle paths can only pass STA with manual intervention which is error-prone and re-quires Nuelight to document the zero cycle path and provide an exception file for STA when one exists within a RIP or bolt-on.

RTL DESIGN GUIDELINES

 

[gck]

Hi,

Check out the timing constraints for the specific Vendor software. You should have something for False path.
For Xilinx ISE, TIG - Timing Ignore is the timing constraint which is useful.

If you use this then, path will be ignored and you won't get any error for this.

Hope this helps you out