when AE goes high, data can be shifted into the register. the last 22b shifted through are then registered when AE transitions low.
This has implications that AE should normally be low, and should transition high when a new address is to be loaded. many SPI designs are not this way.
The data is shifted in MSB first. not all serial protocols use this method.
in your case, shifting 24 bits in, the upper 2 bits are unimportant and can be 1 or 0 (as long as the shift-out is unused). likewise shifting 32b into the unit can be done if the upper 10b (the first 10 bits transmitted) are "don't cares" and the last 22b shifted out are the address, with the LSB being the last bit transmitted. these upper 10b are shifted out of the device, if that pin is connected to anything.
AE cannot transition until the end of an address update. and SPI controller might send 8b at a time, toggling its CS (the AE signal here) multiple times per transmission. If a microcontroller's SPI interface is used, you must either set the CS line to stay high during the address transmission, or you must add code and make the AE line be GPIO.
finally, the data to the shift register is clocked by the rising edge of the serial clock. Further, setup/hold times must be met. This can be an issue if the clock polarity is incorrect, as the data might change at the same time as the clock. (among other things)