Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

well tap,deecap,teecap cells

Status
Not open for further replies.

avinashbaba

Newbie level 5
Joined
Feb 11, 2011
Messages
9
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,338
hey what are well tap, deecap, tee cap cells in physical design.
where we use them for and what should be the minimum distance between well tap cells and when a vertical metal layer included what will the distance to be given b/w successive well taps.
 

avinash,

Well tap: contact ponits which are heavily doped : A P-type substrate "tap" is connected to VSS and an N-type n-well tap is connected to VDD to prevent latchup.
D-Cap: This cells are usefull to reduce voltage peaks
tie cells: available in verilog netlist which are nothing but cells with one of their ports fixed at 1(VDD) or 0(gnd)

and for the design rules please refer your technology file
 
Hi pavan,

can u please elaborate on the D-cap cells regarding their position and size parameters.
 

Hi avinash,

3% and 8% of the core physical area is required for the decoupling capacitors. This is referred to as the “dcap density”. For worst cases decoupling capacitance comes entirely from dedicated Cox (gate oxide capacitance) sources.

Designs using DSM technologies now require the power grid voltage drop to be much less than 10% of Vdd. To achieve this goal, decoupling capacitors are added to minimize switching noise. The charge held by dcap is used to ensure voltage stability during the high-speed switching events that charge and discharge.

Dcap cells can be added incrementally as needed. The number of dcaps can be estimated and then placed based on intermediate power density analysis results and IR drop analysis results. This will most likely be done at the ECO cell and filler insertion stage.

Decoupling capacitors are inserted in a two step approach. The first step consists of inserting dcaps before the standard cells are placed. This will ensure proper distribution of dcaps in the design before timing driven placement cause clumping that can prevent even distribution of dcaps. The second step is done post-route to add decoupling capacitors where necessary based on power rail analysis.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top