reading your email I understand that you are a newbie to VHDL and FPGA/CPLD design, is that right?
In that case you need some basis before you fry a chip. I would suggest you to have a look to some tutorials (search in this group) of VHDL and FPGA/CPLD design.
Basic steps :roll: :
1) write your VHDL for the counter
2) simulate it
3) synthesize it
4) P&R it, for this you need to map it first using a UCF (User Constraint File), this file is where you write the LOC (location) of your pins, where your internal signals are connected.
Good luck,
- maestor