Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

.13 vs .18 process - some ideas needed

Status
Not open for further replies.

kinysh

Member level 3
Joined
Jul 16, 2002
Messages
65
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
509
tsmc wire load model

Hi all:

I am evaluate the .13 process vs .18 process
.13 using tsmc
.18 using umc

after synthesize the same code with same script.
the worse case in .13 is even slower than the worse case in .18

any one have any idea? 8O 8O
is it because the worse case is too worst for .13?

bests
kinysh
 

kvsidhi

Newbie level 5
Joined
Apr 23, 2003
Messages
9
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
87
Hi ,
Generally Synthesis tool looks more delay between nets when it shifts from 0.18 to 0.13 u technology. (tool takes more delay for wire delays).
This may be the case you are getting worser delay. :!:

Let me know whether you are talking about logical synthesis or physical synthesis.

Regards,
-Sidhi
 

flatulent

Advanced Member level 5
Joined
Jul 19, 2002
Messages
4,629
Helped
489
Reputation
980
Reaction score
150
Trophy points
1,343
Location
Middle Earth
Activity points
46,689
more clues

Another thing to try is using the average case and best case simulations. Are they slower in the smaller dimension case?
 

kinysh

Member level 3
Joined
Jul 16, 2002
Messages
65
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
509
:D :D :D :D :D
Thanks for your information.
I use DC compile only.
and after I change the wire load model from tsmc13_wl50 to tsmc13_wl10. it is much faster in worst case.
.18 process:: slack -0.28 clock 150Mhz
.13 process:: slack -0.32 clock 200Mhz
I use the wrong wire load model. TSMC's wire load model is really conservative, its smallest wire load model is equal to the second largest wire load model in my other .18 library.

following is the wire load model.
can you tell me what is the unit-length, is it .13um ? it is not in the report_lib.

If I use typical case the temprature is only 25 C. not good for real situation.
when you do synthesys, if you use typical case/best case. how do you treat worst case?


Bests
qysheng


Wire Loading Model:

Name : tsmc13_wl10
Location : typical
Resistance : 8.5e-08
Capacitance : 0.00015
Area : 0.7
Slope : 66.667
Fanout Length Points Average Cap Std Deviation
--------------------------------------------------------------
1 66.67

Name : tsmc13_wl50
Location : typical
Resistance : 8.5e-08
Capacitance : 0.00015
Area : 0.7
Slope : 333.335
Fanout Length Points Average Cap Std Deviation
--------------------------------------------------------------
1 333.33
 

maniasonic

Member level 1
Joined
Jan 8, 2004
Messages
34
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Activity points
238
but you must be sure that you are using a right wire load model. if you are not sure, pls consult the library vendor or foundry people for help.
 

CatKing

Full Member level 3
Joined
Jun 5, 2001
Messages
157
Helped
3
Reputation
6
Reaction score
2
Trophy points
1,298
Activity points
1,129
have you eval the mask cost of these 2 processes?
maybe 8x difference...
 

melonpy

Junior Member level 1
Joined
Dec 29, 2003
Messages
16
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
238
kinysh said:
:D :D :D :D :D
Thanks for your information.
I use DC compile only.

If I use typical case the temprature is only 25 C. not good for real situation.
when you do synthesys, if you use typical case/best case. how do you treat worst case?


Bests
qysheng


Wire Loading Model:

Name : tsmc13_wl10
Location : typical
Resistance : 8.5e-08
Capacitance : 0.00015
Area : 0.7
Slope : 66.667
Fanout Length Points Average Cap Std Deviation
--------------------------------------------------------------
1 66.67

Name : tsmc13_wl50
Location : typical
Resistance : 8.5e-08
Capacitance : 0.00015
Area : 0.7
Slope : 333.335
Fanout Length Points Average Cap Std Deviation
--------------------------------------------------------------
1 333.33
I dont't know if you use typical or fast model? For synthesis and timing optimizing, we should use slow model for better timing result.
 

mark_yeh

Newbie level 6
Joined
Nov 11, 2004
Messages
12
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
108
Re: .13 vs .18

i don't think the timing report is precision, espcially in .13 process. you should get the sdf file and back-annotate to the netlist. and then you can compare the tow timing reports, and get the result correctly.
 

eda_wiz

Advanced Member level 2
Joined
Nov 7, 2001
Messages
654
Helped
57
Reputation
114
Reaction score
29
Trophy points
1,308
Activity points
6,195
.13 vs .18

wireload model should be used based on the area of the design.. for designs with area less than 10kgates you can use tsmc13_wl10.. for designs with area 40k-50k you should use tsmc13_wl50...

But it is always better to build a custom wireload model for more accuracy
 

AlexWan

Full Member level 5
Joined
Dec 26, 2003
Messages
304
Helped
8
Reputation
16
Reaction score
2
Trophy points
1,298
Activity points
2,692
.13 vs .18

Physical Compiler is better tool for synthesis for .13.
No wireload model, the result of DC with cell delay is not exact.
 

visualart

Advanced Member level 1
Joined
Dec 21, 2001
Messages
467
Helped
28
Reputation
56
Reaction score
4
Trophy points
1,298
Activity points
3,336
.13 vs .18

in my opinion, you ought run the physical synthesis, add the layout information to revise the delay.
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top