.13 vs .18 process - some ideas needed

[kinysh]

tsmc wire load model

Hi all:

I am evaluate the .13 process vs .18 process
.13 using tsmc
.18 using umc

after synthesize the same code with same script.
the worse case in .13 is even slower than the worse case in .18

any one have any idea? 8O 8O
is it because the worse case is too worst for .13?

bests
kinysh

 

[kvsidhi]

Hi ,
Generally Synthesis tool looks more delay between nets when it shifts from 0.18 to 0.13 u technology. (tool takes more delay for wire delays).
This may be the case you are getting worser delay. :!:

Let me know whether you are talking about logical synthesis or physical synthesis.

Regards,
-Sidhi

 

[flatulent]

more clues

Another thing to try is using the average case and best case simulations. Are they slower in the smaller dimension case?

 

[kinysh]

Thanks for your information.
I use DC compile only.
and after I change the wire load model from tsmc13_wl50 to tsmc13_wl10. it is much faster in worst case.
.18 process:: slack -0.28 clock 150Mhz
.13 process:: slack -0.32 clock 200Mhz
I use the wrong wire load model. TSMC's wire load model is really conservative, its smallest wire load model is equal to the second largest wire load model in my other .18 library.

following is the wire load model.
can you tell me what is the unit-length, is it .13um ? it is not in the report_lib.

If I use typical case the temprature is only 25 C. not good for real situation.
when you do synthesys, if you use typical case/best case. how do you treat worst case?


Bests
qysheng


Wire Loading Model:

Name : tsmc13_wl10
Location : typical
Resistance : 8.5e-08
Capacitance : 0.00015
Area : 0.7
Slope : 66.667
Fanout Length Points Average Cap Std Deviation
--------------------------------------------------------------
1 66.67

Name : tsmc13_wl50
Location : typical
Resistance : 8.5e-08
Capacitance : 0.00015
Area : 0.7
Slope : 333.335
Fanout Length Points Average Cap Std Deviation
--------------------------------------------------------------
1 333.33

 

[maniasonic]

but you must be sure that you are using a right wire load model. if you are not sure, pls consult the library vendor or foundry people for help.

 

[CatKing]

have you eval the mask cost of these 2 processes?
maybe 8x difference...

 

[melonpy]

Thanks for your information.
I use DC compile only.

If I use typical case the temprature is only 25 C. not good for real situation.
when you do synthesys, if you use typical case/best case. how do you treat worst case?


Bests
qysheng


Wire Loading Model:

Name : tsmc13_wl10
Location : typical
Resistance : 8.5e-08
Capacitance : 0.00015
Area : 0.7
Slope : 66.667
Fanout Length Points Average Cap Std Deviation
--------------------------------------------------------------
1 66.67

Name : tsmc13_wl50
Location : typical
Resistance : 8.5e-08
Capacitance : 0.00015
Area : 0.7
Slope : 333.335
Fanout Length Points Average Cap Std Deviation
--------------------------------------------------------------
1 333.33

I dont't know if you use typical or fast model? For synthesis and timing optimizing, we should use slow model for better timing result.

 

[mark_yeh]

Re: .13 vs .18

i don't think the timing report is precision, espcially in .13 process. you should get the sdf file and back-annotate to the netlist. and then you can compare the tow timing reports, and get the result correctly.

 

[eda_wiz]

.13 vs .18

wireload model should be used based on the area of the design.. for designs with area less than 10kgates you can use tsmc13_wl10.. for designs with area 40k-50k you should use tsmc13_wl50...

But it is always better to build a custom wireload model for more accuracy

 

[AlexWan]

.13 vs .18

Physical Compiler is better tool for synthesis for .13.
No wireload model, the result of DC with cell delay is not exact.

 

[visualart]

.13 vs .18

in my opinion, you ought run the physical synthesis, add the layout information to revise the delay.